
[ASAHI KASEI] [AK4544A]
<MS0026-E-00> - 7 -
Switching Characteristics
Ta=25
°
C, AVdd=5.0V
±
5%, DVdd=3.3V
±
5% or 5V
±
5%, 50pF external load
Parameter
Master Clock Frequency Note)
If Crystal is not used.
AC link Interface Timing
BIT_CLK frequency
BIT_CLK clock Period(Tbclk=1/Fbclk)
BIT_BLK low pulse width
BIT_BLK low pulse width
BIT_CLK rise time
BIT_CLK fall time
SYNC frequency
SYNC low pulse width
Symbol
Fmclk
Min
-
45
Typ
24.576
50
max
-
55
Units
MHz
%
Fbclk
Tbclk
Tclk_low
Tclk_high
Trise_clk
Tfall_clk
-
36
36
-
-
-
-
12.288
81.38
40.7
40.7
-
-
48
19.5
(240 cycle)
1.3
(16 cycle)
-
-
-
-
-
45
45
6
6
-
-
MHz
ns
ns
ns
ns
ns
kHz
μ
s
(Tbclk)
μ
s
(Tbclk)
ns
ns
ns
ns
ns
SYNC high pulse width
SYNC rise time
SYNC fall time
Setup time(SYNC, SDATA_OUT)
Hold time(SYNC, SDATA_OUT)
SDATA_IN delay time from BIT_CLK
rising edge
SDATA_IN rise time
SDATA_IN fall time
SDATA_OUT rise time
SDATA_OUT fall time
Cold Rest
(SDATA_OUT=L, SYNC=L)
RESET# active low pulse width
RESET# inactive to BIT_CLK delay
Tsync_low
Tsync_high
Trise_sync
Tfall_sync
Tsetup
Thold
Tdelay
-
-
-
-
6
6
-
-
Trise_din
Tfall_din
Trise_dout
Tfall_dout
10
25
-
-
-
-
-
-
-
-
-
15
6
6
6
6
ns
ns
ns
ns
Trst_low
Trst2clk
1.0
162.8
(2 cycle)
-
-
μ
s
ns
(Tbclk)
Warm Rest Timing
SYNC active low pulse width
SYNC inactive to BIT_CLK delay
Tsync_high
Tsync2clk
1.0
162.8
(2 cycle)
1.3
(16 cycle)
-
μ
s
(Tbclk)
ns
(Tbclk)
AC-link L ow Power Mode Timing
End of Slot 2 to BIT_CLK , SDATA_IN
Low
Activate Test Mode Timing
Setup to trailing edge of RESET#
Hold from RESET# rising edge
Rising edge of RESET# to Hi-Z
Falling edge of RESET# to “L”
Note ) The use of a crystal is recommended. If master clock is supplied from controller (or if a external oscillator is
used), Master Clock should be input to XTAL_IN, meanwhile XTAL_OUT should be open.
Ts2_pdwn
-
-
1.0
μ
s
Tsetup2rst
Thold2rst
Toff
Tlow
15.0
100
-
-
-
-
-
-
-
-
50
50
ns
ns
ns
ns