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參數(shù)資料
| 型號： | AK4544AVQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | CABLE ASSEMBLY; BNC MALE TO N MALE; 50 OHM, RG223/U COAX, DOUBLE SHIELDED; 36" CABLE LENGTH |
| 中文描述： | AC97多媒體音頻編解碼器與SRC |
| 文件頁數(shù)： | 23/35頁 |
| 文件大小： | 381K |
| 代理商： | AK4544AVQ |
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[ASAHI KASEI] [AK4544A]
<MS0026-E-00> - 23 -
n
Extended Audio ID(Index 28h)
The Extended Audio ID(28h) is a read only register. 2bits D15&D14 can be read for codec identification. D15,14 are
automatically set with the codec ID1# pin(46pin) and ID0# pin(45pin). ID1# pin and ID0# pin can be strapped and
adopt inverted polarity and these logic values are stored to D15 and D14 called as ID1 bit and ID0 bit. Default ID
(ID1,ID0)=(0,0) when both ID1# pin and ID0# pin are open state. Depended on codec ID configuration, the AK 4544A
is assigned to Primary codec or Secondary codec. Note that codec ID configuration has to be fixed before Powering up
of the device.
Physical Connection
Pin46(ID1#)
NC
NC
GND
GND
Logic Value
ID1
0
0
1
1
Pin45(ID0#)
NC
GND
NC
GND
ID0
0
1
0
1
Configuration
Primary
Secondary ID01
Secondary ID10
Secondary ID11
The AMAP bit D9 of this read only register for the AK 4544A will always be set to “1” indicating that the
default(following cold or warm reset) codec slot DAC mapping(configured via hardwiring, strap pin(s), or other
methods) conform to below table.
The audio DAC mapping can be changed based on the codec ID configuration.
AC-link Frame Data used for DACs
PCM Left DAC uses
data from Slot No.
3
3
7
6
Since AK 4544A supports variable sample rates, field of D0: VRA is set to 1, indicates Variable Rate PCM Audio is
supported.
Codec ID
PCM Right DAC uses
data from Slot No.
4
4
8
9
Comments
00
01
10
11
Original Definition(Master)
Original Definition(Docking)
Left/Right surround channels
Center/LFE channels
n
Extended Audio Status and Control Register (Index 2Ah)
Bits D0 to D3, and D11 to D14 are read/write controls, while D6 to D9 are read only data to controller.
Bit
Function
VRA=1
(D0)
Control Registers and tag-bit/SLOTREQ signaling
Because CDAC,LDAC,SDAC, and MICADC are not supported, default value at cold register reset for D11-D14 is set
to “0”.
Internal SRC related circuits are controlled by this VRA bit(2Ah), not by VRA in Extended Audio ID register(28h).
Enables Variable Rate Audio mode in conjunction with Audio Sample Rate
相關PDF資料 |
PDF描述 |
|---|---|
| AK4544 | AC97 MULTIMEDIA AUDIO CODEC WITH SRC |
| AK4545 | AC97 AUDIO CODEC WITH SRC AND DIT |
| AK4545VQ | AC97 AUDIO CODEC WITH SRC AND DIT |
| AK4551 | LOW POWER & SMALL PACKAGE 20BIT CODEC |
| AK4551VT | LOW POWER & SMALL PACKAGE 20BIT CODEC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK4545 | 制造商:AKM 制造商全稱:AKM 功能描述:AC97 AUDIO CODEC WITH SRC AND DIT |
| AK4545VQ | 制造商:AKM 制造商全稱:AKM 功能描述:AC97 AUDIO CODEC WITH SRC AND DIT |
| AK4550 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.C FOR AK4550 |
| AK4550VT | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER & SMALL PACKAGE 16BIT CODEC |
| AK4550VT-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
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