
ASAHI KASEI
[AK4536]
MS0174-E-00
2002/09
- 34 -
n
SPK-ALC Operation
The ALC (Automatic Level Control) operation of speaker output is done by ALC2 block when ALC2 bit is “1”. Input
resistance of the ALC2 is 24k
(typ) and centered around VCOM voltage. The ALC2 level diagram is shown in Figure 30.
The limiter detection level is proportional to SVDD voltage. The output level is limited by the ALC2 circuit when the input
signal exceeds –5.2dBV (=FS-2.1dB@AVDD=SVDD=3.3V). When a continuous signal of –5.2dBV or greater is input to
the ALC2 circuit, the change period of the ALC2 limiter operation is 250
μ
s (=2/fs@fs=8kHz) and the attenuation level is
0.5dB/step.
The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the
input level of the Speaker-amp goes to –7.2dBV(=FS-4.1dB@AVDD=SVDD=3.3V).
Maximum gain of the ALC2
recovery operation is +18dB.
When the input signal is between –5.2dBV and –7.2dBV, the ALC2 limiter or recovery operations are not done.
When the PMSPK bit changes from “0” to “1”, the initilization cycle (512/fs = 64ms @fs=8kHz at ROTM bit = “0”) starts.
The ALC2 is disabled during the initilization cycle and the ALC2 starts after completing the initilization cycle.
The ROTM bit is set during the PMSPK bit = “0”.
When the ALC2 is disable, a gain of the ALC2 block is fixed to –2dB. Therefore, a gain of internal speaker block is +4dB
(Full-differential output) at SPKG bit = “0”, and it is +6.24dB (Full-differential output) at SPKG bit = “1”.
Parameter
ALC2 Limiter operation
Operation Start Level
5.2dBV
fs=8kHz
2/fs = 250
μ
s
Period
fs=16kHz
2/fs = 125
μ
s
Zero-crossing Detection
No
ATT/GAIN
0.5dB step
Table 17. Limiter /Recovery of ALC2 (ROTM bit = “0”)
ALC2 Recovery operation
7.2dBV
512/fs=64ms
512/fs=32ms
Yes (Timeout = Period Time)
1dB step
-15.1dBV
FS
FS-12dB
0dBV
FS-2.1dB = -5.2dBV
-1.2dBV
Full-differential
-3.1dBV
-10dBV
-5.2dBV
-20dBV
-30dBV
-23.1dBV
-8dB
-15.1dBV
-11.1dBV
-3.1dBV
FS-4.1dB = -7.2dBV
+7.9dB
+15.9dB
+3.9dB
-2.1dB
+6.0dB
-8dB
Single-ended
DVOL
DAC
ALC2
SPK-AMP
0.8dBV
+6.0dB
Figure 30. Speaker-Amp Output Level Diagram (SVDD=3.3V, DVOL=
8.0dB, SPKG bit = “0”)
* FS = Full Scale