參數(shù)資料
型號(hào): AK4536
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16-Bit Mono CODEC with ALC & MIC/SPK-AMP
中文描述: 16位單聲道編解碼器ALC的
文件頁(yè)數(shù): 31/59頁(yè)
文件大?。?/td> 403K
代理商: AK4536
ASAHI KASEI
[AK4536]
MS0174-E-00
2002/09
- 31 -
[3] Example of ALC1 Operation
Table 15 shows the examples of the ALC1 setting.
fs=8kHz
fs=16kHz
Data
1
00
0
01
Register Name Comment
Data
1
00
0
00
Operation
-4dBFS
Don’t use
Enable
16ms
Operation
-4dBFS
Don’t use
Enable
16ms
LMTH
LTM1-0
ZELM
ZTM1-0
Limiter detection Level
Limiter operation period at ZELM = 1
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
Gain of IPGA
Limiter ATT Step
Recovery GAIN Step
ALC1 Enable bit
WTM1-0
00
16ms
01
16ms
REF6-0
IPGA6-0
LMAT1-0
RATT
ALC1
47H
47H
00
0
1
+27.5dB
+27.5dB
1 step
1 step
Enable
47H
47H
00
0
1
+27.5dB
+27.5dB
1 step
1 step
Enable
Table 15. Examples of the ALC1 Setting
The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1
operation is finished by ALC1 bit = “0” or PMMIN bit = “0”.
LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits
Manual Mode
* The value of IPGA should be
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (REF6-0)
WR (IPGA6-0)
ALC1 Operation
WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 1
Maximum Gain = +27.5dB
Limiter Detection Level = -4dBFS
ALC2 bit = “1” (default)
(1) Addr=06H, Data=00H
(2) Addr=08H, Data=47H
(4) Addr=07H, Data=61H
(3) Addr=09H, Data=47H
Note : WR : Write
Figure 28. Registers set-up sequence at the ALC1 operation
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