
ASAHI KASEI
[AK4536]
MS0174-E-00
2002/09
- 10 -
Parameter
PLL Slave Mode (PLL Reference Clock = BICK pin) (See Figure 6, Figure 7, Figure 8 and Figure 9)
FCK Frequency
Pulse width High
BICK Period (PLL2-0 = “001”)
(PLL2-0 = “010”)
(PLL2-0 = “011”)
BICK Pulse Width Low
Pulse Width High
FCK “
↑
” to BICK “
↑
” (Note 21)
FCK “
↑
” to BICK “
↓
” (Note 22)
BICK “
↑
” to FCK “
↑
” (Note 21)
BICK “
↓
” to FCK “
↑
” (Note 22)
BICK “
↑
” to SDTO (BCKP = “0”)
BICK “
↓
” to SDTO (BCKP = “1”)
SDTI Hold Time
SDTI Setup Time
EXT Slave Mode (See Figure 10 and Figure 11)
MCKI Frequency: 256fs
512fs
1024fs
Pulse Width Low
Pulse Width High
AC Pulse Width (Note 23)
FCK Frequency (MCKI = 256fs or 512fs)
(MCKI = 1024fs)
Duty
BICK Period
BICK Pulse Width Low
Pulse Width High
FCK Edge to BICK “
↑
” ” (Note 24)
BICK “
↑
” to FCK Edge (Note 24)
FCK to SDTO (MSB) (Except I
2
S mode)
BICK “
↓
” to SDTO
SDTI Hold Time
SDTI Setup Time
Note 21. MSBS, BCKP bits = “00” or “11”
Note 22. MSBS, BCKP bits = “01” or “10”
Note 23. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 3)
Note 24. BICK rising edge must not occur at the same time as FCK edge.
Symbol
min
typ
max
Units
fFCK
tFCKH
tBCK
tBCK
tBCK
tBCKL
tBCKH
tFCKB
tFCKB
tBFCK
tBFCK
tBSD
tBSD
tSDH
tSDS
7.35
tBCK-60
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
60
60
26
1/fFCK-tBFCK
80
80
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/16fFCK
1/32fFCK
1/64fFCK
fCLK
fCLK
fCLK
tCLKL
tCLKH
tACW
fFCK
fFCK
duty
tBCK
tBCKL
tBCKH
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
0.4/fCLK
7.35
7.35
45
600
240
240
2.048
4.096
8.192
8
8
6.656
13.312
13.312
26
13
55
MHz
MHz
MHz
ns
ns
ns
kHz
kHz
%
ns
ns
ns
tFCKB
tBFCK
tFSD
tBSD
tSDH
tSDS
50
50
50
50
80
80
ns
ns
ns
ns
ns
ns