- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385092 > AK4534 (Asahi Kasei Microsystems Co.,Ltd) 16Bit CODEC with MIC/HP/SPK-AMP PDF資料下載
參數(shù)資料
| 型號： | AK4534 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16Bit CODEC with MIC/HP/SPK-AMP |
| 中文描述： | 16位編解碼器麥克風/惠普/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 48/64頁 |
| 文件大?。?/td> | 443K |
| 代理商： | AK4534 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁當前第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
ASAHI KASEI
[AK4534]
MS0133-E-03
2003/5
- 48 -
Addr
09H
Register Name
ALC Mode Control 1
R/W
Default
D7
0
RD
0
D6
ALC2
R/W
1
D5
ALC1
R/W
0
D4
D3
D2
D1
RATT
R/W
0
D0
ZELM
R/W
0
LMAT1
R/W
0
LMAT0
R/W
0
LMTH
R/W
0
LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 26)
The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about
±
2dB.
Default is “0”.
LMTH
0
1
ALC1 Limiter Detection Level
ADC Input
≥
6.0dBFS
ADC Input
≥
4.0dBFS
Table 26. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
ALC1 Recovery Waiting Counter Reset Level
6.0dBFS
>
ADC Input
≥
8.0dBFS
4.0dBFS
>
ADC Input
≥
6.0dBFS
Default
RATT: ALC1 Recovery GAIN Step (see Table 27)
During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For example,
when the current IPGA value is 30H and RATT bit = “1” is set, the IPGA changes to 32H by the ALC1 recovery
operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the
reference level (REF6-0 bits), the IPGA value does not increase.
RATT
0
1
Table 27. ALC1 Recovery Gain Step Setting
GAIN STEP
1
2
Default
LMAT1-0: ALC1 Limiter ATT Step (see Table 28)
During the ALC1 limiter operation, when either Lch or Rch exceeds the ALC1 limiter detection level set by LMTH,
the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value is
47H and the LMAT1-0 bits = “11”, the IPGA transition to 43H when the ALC1 limiter operation starts, resulting
in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds IPGA = “00”
(
8dB), it clips to “00”.
LMAT1
0
0
1
1
LMAT0
0
1
0
1
ATT STEP
1
2
3
4
Default
Table 28. ALC1 Limiter ATT Step Setting
ZELM: Enable zero crossing detection at ALC1 Limiter operation
0: Enable (Default)
1: Disable
When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently and the
IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1 recovery
operation. When the ZELM bit = “1”, the IPGA value is changed immediately.
ALC1: ALC1 Enable Flag
0: ALC1 Disable (Default)
1: ALC1 Enable
ALC2: ALC2 Enable Flag
0: ALC2 Disable
1: ALC2 Enable (Default)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4534VN | 16Bit CODEC with MIC/HP/SPK-AMP |
| AK4536 | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4536VN | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4537 | 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4537VN | 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4534VN | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit CODEC with MIC/HP/SPK-AMP |
| AK4534VQ | 功能描述:IC CODEC 16BIT MIC/HP/SPK-AMP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購買時間 標準包裝:1,000 |
| AK4536 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4536VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4537 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP |
發(fā)布緊急采購，3分鐘左右您將得到回復。