參數(shù)資料
型號(hào): AK4534
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16Bit CODEC with MIC/HP/SPK-AMP
中文描述: 16位編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù): 11/64頁
文件大小: 443K
代理商: AK4534
ASAHI KASEI
[AK4534]
MS0133-E-03
2003/5
- 11 -
Parameter
Control Interface Timing (4-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “
” to CCLK “
CCLK “
” to CSN “
CDTO Delay
CSN “
” to CDTO Hi-Z
Control Interface Timing (I
2
C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 26)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Symbol
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
min
200
80
80
40
40
150
50
50
typ
max
50
70
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
1/fs
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
-
4.7
4.0
4.7
4.0
4.7
0
0.25
-
-
4.0
0
100
-
-
-
-
-
-
-
1.0
0.3
-
50
Reset Timing
PDN Pulse Width (Note 27)
PMADC “
” to SDTO valid (Note 28)
Note 26. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 27. The AK4534 can be reset by the PDN pin = “L”.
Note 28. This is the count of LRCK “
” from the PMADC bit = “1”.
Purchase of Asahi Kasei Microsystems Co., Ltd I
2
C components conveys a license under the Philips I
2
C
patent to use the components in the I
2
C system, provided the system conform to the I
2
C specifications
defined by Philips.
tPD
tPDV
150
2081
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