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參數資料
| 型號： | AK4534 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16Bit CODEC with MIC/HP/SPK-AMP |
| 中文描述： | 16位編解碼器麥克風/惠普/胰腎聯合移植腺苷 |
| 文件頁數： | 35/64頁 |
| 文件大?。?/td> | 443K |
| 代理商： | AK4534 |
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ASAHI KASEI
[AK4534]
MS0133-E-03
2003/5
- 35 -
(2) I
2
C-bus Control Mode (I2C pin = “H”)
The AK4534 supports the standard-mode I
2
C-bus (max: 100kHz). The AK4534 does not support a fast-mode I
2
C-bus
system (max: 400kHz).
(2)-1. WRITE Operations
Figure 20 shows the data transfer sequence for the I
2
C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 26). After the START
condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit (R/W). The
most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0 (device address
bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 and CAD0 pins) set these
device address bits (Figure 21). If the slave address matches that of the AK4534, the AK4534 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line
(HIGH) during the acknowledge clock pulse (Figure 27). A R/W bit value of “1” indicates that the read operation is to be
executed. A “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4534. The format is MSB first, and those most significant
3-bits are fixed to zeros (Figure 22). The data after the second byte contains control data. The format is MSB first, 8bits
(Figure 23). The AK4534 generates an acknowledge after each byte has been received. A data transfer is always terminated
by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a
STOP condition (Figure 26).
The AK4534 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4534
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 0FH prior to
generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. In
order to ensure proper operation, write “00H” to registers 0EH and 0FH test registers.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 28) except for the START and STOP conditions.
SDA
Slave
Address
S
S
T
A
R
T
R/W="0"
A
C
K
Sub
Address(n)
A
C
K
Data(n)
A
C
K
Data(n+1)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
S
T
O
P
Figure 20. Data Transfer Sequence at the I
2
C-Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 21. The First Byte
0
0
0
A4
A3
A2
A1
A0
Figure 22. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 23. Byte Structure after the second byte
相關PDF資料 |
PDF描述 |
|---|---|
| AK4534VN | 16Bit CODEC with MIC/HP/SPK-AMP |
| AK4536 | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4536VN | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4537 | 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP |
| AK4537VN | 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AK4534VN | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit CODEC with MIC/HP/SPK-AMP |
| AK4534VQ | 功能描述:IC CODEC 16BIT MIC/HP/SPK-AMP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購買時間 標準包裝:1,000 |
| AK4536 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4536VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4537 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP |
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