參數(shù)資料
型號(hào): AK4528
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC
中文描述: 高性能24位96kHz的音頻編解碼器
文件頁(yè)數(shù): 25/29頁(yè)
文件大小: 284K
代理商: AK4528
ASAHI KASEI
[AK4528]
MS0011-E-00
2000/1
- 25 -
2. Voltage Reference
The differential voltage between VREF and AGND sets the analog input/output range. VREF pin is normally connected to
VA with a 0.1μF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2μF parallel with a
0.1μF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be
drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to
avoid unwanted coupling into the AK4528.
3. Analog Inputs
The IPGA inputs are single-ended and the input resistance 27k
W
(typ. @fs=44.1kHz). The input signal range scales with
the VREF voltage and nominally 0.56 x VREF Vpp. It is recommended that the input DC bias voltage is 0.56VA
~
0.60VA
as centered in the internal common voltage about VA/2). The AK4528 can accept input voltages from AGND to VA. The
ADC output data format is 2’s complement. The output code is 7FFFFFH(@24bit) for input above a positive full scale and
800000H(@24bit) for input below a negative fill scale. The ideal code is 000000H(@24bit) with no input signal. The DC
offset including ADC own DC offset removed by the internal HPF(fc=0.9Hz@fs=44.1kHz).
The AK4528 samples the analog inputs at 64fs. The digital filter rejects noise above the stopband except for multiples of
64fs. A simple RC filter may be used to attenuate any noise around 64fs though most audio signals do not have significant
energy at 64fs. Figure 12 is an example of differential input circuit.
AK4528
AINR+
1.5nF
330
+
Vop+/-=+/-15V
Signal
10k
330
0.1
μ
22
μ
4.7k
4.7k
5.96Vpp
2.8Vpp
2
3
4
5
AINR-
AINL-
AINL+
4.7k
Vop+
4.7k
VA
3.3k
10
μ
BIAS
Same circuit
2.8Vpp
NJM5532
+
+
-
-
Vop-
VA=5V
Input RC filter response : fc = 160kHz, g = -0.07dB at 20kHz, -0.26dB at 40kHz.
Figure 12. Differential Input Buffer Example
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