參數(shù)資料
型號(hào): AK4528
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC
中文描述: 高性能24位96kHz的音頻編解碼器
文件頁數(shù): 16/29頁
文件大小: 284K
代理商: AK4528
ASAHI KASEI
[AK4528]
MS0011-E-00
2000/1
- 16 -
n
Power Down & Reset
The ADC and DAC of AK4528 are placed in the power-down mode by bringing a power down pin(PDN)=“L” and each
digital filter is also reset at the same time. The internal register values are initialized by PDN=“L”. This reset should always
be done after power-up.
In case of serial mode, the default value of both control registers for ADC and DAC are in reset state (RSTADN=
RSTDAN = ”0” ), each register sholud be cancelled after doing the needed setting. In case of the ADC, an analog
initialization cycle starts after exiting the power-down or reset state. Therefore, the output data, SDTO becomes available
after 516 cycles of LRCK. In case of DAC, the initialization cycle starts after PDN= “H” or PWVR bit = “1”. The power
down mode can be also controlled by the registers (PWAD, PWDA).
Power Supply
RSTADN(registe
RSTDAN(registe
PWAD(register)
PWDA(register)
PWVR(register)
ADC Internal State
SDTO
OATT
AOUT
DAC Internal State
External Mute
Example
External clocks
The clocks can be stopped.
PD
Reset INITA
Normal
PD
INITA
Normal
“0”
“0”
Output
Output
PD
Reset
PD
Normal
Normal
00H
00H
XXH
XXH
00H
00H
XXH
XXH
“0”
FI
Output
FI
MCLK, LRCK, BICK
PDN pin
*
*
*
INITD
*
Hi-Z
Hi-Z
Output
PD
Normal
00H
00H
XXH
512/fs
XXH
FI
*
*
Hi-Z
Output
PD
“0”
512/fs
INITD
·
INITA:
·
INITD:
·
PD:
·
XXH:
·
FI:
·
AOUT:
Initializing period of ADC analog section (516/fs).
Initializing period of DAC analog section (512/fs).
Power down state. In case of PDN= “L”, the contents of all registers are initialized, otherwise hold.
The current value in ATT register.
Fade in. After exiting power down and reset state, ATT value fades in by 8032/fs cycles(max).
Some pop noise may occur at “*”.
Figure 7. Reset & Power down sequence in Serial Mode
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