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參數資料
| 型號： | AK4527B |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC |
| 中文描述： | 高性能多通道音頻解碼器 |
| 文件頁數： | 6/33頁 |
| 文件大?。?/td> | 292K |
| 代理商： | AK4527B |
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ASAHI KASEI
[AK4527B]
MS0056-E-00
2000/10
- 6 -
No.
23
24
25
26
27
28
29
30
31
32
33
Pin Name
LOUT3
ROUT3
LOUT2
ROUT2
LOUT1
ROUT1
LIN-
LIN+
RIN-
RIN+
DZF2
I/O
O
O
O
O
O
O
I
I
I
I
O
Function
DAC3 Lch Analog Output Pin
DAC3 Rch Analog Output Pin
DAC2 Lch Analog Output Pin
DAC2 Rch Analog Output Pin
DAC1 Lch Analog Output Pin
DAC1 Rch Analog Output Pin
Lch Analog Negative Input Pin
Lch Analog Positive Input Pin
Rch Analog Negative Input Pin
Rch Analog Positive Input Pin
Zero Input Detect 2 Pin (Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”.
Analog Input Overflow Detect Pin (Note 3)
This pin goes to “H” if the analog input of Lch or Rch is overflows.
Common Voltage Output Pin, AVDD/2
Large external capacitor around 2.2μF is used to reduce power-supply noise.
Positive Voltage Reference Input Pin, AVDD
Analog Power Supply Pin, 4.5V
～
5.5V
Analog Ground Pin, 0V
Zero Input Detect 1 Pin (Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”.
Master Clock Input Pin
Parallel/Serial Select Pin
“L”: Serial control mode, “H”: Parallel control mode
Audio Data Interface Format 0 Pin in parallel control mode
Chip Select Pin in 3-wire serial control mode
This pin should be connected to DVDD at I
2
C bus control mode
Audio Data Interface Format 1 Pin in parallel control mode
Control Data Clock Pin in serial control mode
I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I
2
C Bus)
Loopback Mode 0 Pin in parallel control mode
Enables digital loop-back from ADC to 3 DACs.
Control Data Input Pin in serial control mode
I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I
2
C Bus)
Loopback Mode 1 Pin (Note 1)
Enables all 3 DAC channels to be input from SDTI1.
OVF
O
34
VCOM
O
35
36
37
38
VREFH
AVDD
AVSS
DZF1
I
-
-
O
39
40
MCLK
P/S
I
I
DIF0
CSN
I
I
41
DIF1
SCL/CCLK
I
I
42
LOOP0
I
43
SDA/CDTI
I/O
44
LOOP1
I
Notes: 1. SDOS, SMUTE, DFS, and LOOP1 pins are ORed with register data if P/S = “L”.
2. The group 1 and 2 can be selected by DZFM2-0 bits if P/S = “L” and DZFE = “L”.
3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode.
4. All input pins should not be left floating.
相關PDF資料 |
PDF描述 |
|---|---|
| AK4527BVQ | HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC |
| AK4528 | HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC |
| AK4528VF | HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC |
| AK4529 | High Performance Multi-channel Audio CODEC |
| AK4532 | Internet/Network/General Purpose Multimedia Audio CODEC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AK4527BVQ | 制造商:AKM 制造商全稱:AKM 功能描述:HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC |
| AK4528 | 制造商:AKM 制造商全稱:AKM 功能描述:HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC |
| AK4528_04 | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance 24Bit 96kHz Audio CODEC |
| AK4528_12 | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance 24Bit 96kHz Audio CODEC |
| AK4528VF | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance 24Bit 96kHz Audio CODEC |
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