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參數(shù)資料
| 型號： | AK4527B |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC |
| 中文描述： | 高性能多通道音頻解碼器 |
| 文件頁數(shù)： | 22/33頁 |
| 文件大?。?/td> | 292K |
| 代理商： | AK4527B |
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ASAHI KASEI
[AK4527B]
MS0056-E-00
2000/10
- 22 -
n
Serial Control Interface
The AK4527B can control its functions via registers. Internal registers may be written by 2 types of control mode. The
chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default
values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be
initialized. When the state of P/S pin is changed, the AK4527B should be reset by PDN pin.
* Writing to control register is invalid when PDN = “L” or the MCLK is not fed.
* AK4527B does not support the read command.
(1) 3-wire Serial Control Mode (I2C = “L”)
Internal registers may be written to the 3 wire μP interface pins (CSN,CCLK and CDTI). The data on this interface
consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to “1”; Write only), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock
speed of CCLK is 5MHz(max). The CSN pins should be held to “H” except for access.
CDTI
CCLK
CSN
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W:
Read/Write (Fixed to “1” : Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 8. 3-wire Serial Control I/F Timing
(2) I
2
C Bus Control Mode (I2C = “H”)
Internal registers may be written to I
2
C Bus interface pins: SCL & SDA. The data on this interface consists of Chip
address (2bits, CAD0/1), Read/Write (1bit, Fixed to “0”; Write only), Register address (MSB first, 5bits) and
Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of SCL and data is clocked out on
the falling edge. Data can be written after a high-to-low transition of SDA when SCL is “H”(start condition), and is
latched after a low-to-high transition of SDA when SCL is “H”(stop condition). The clock speed of SCL is
100kHz(max). The CSN pin should be connected to DVDD at I
2
C Bus control mode. The AK4527B does not have a
register address auto increment capability.
R/W
ACK
SCL
SDA
0
0
1
0
0
Start
Stop
ACK
ACK
C1 C0
0
0
0 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W:
Read/Write (Fixed to “0” : Write only)
A4-A0: Register Address
D7-D0: Control Data
ACK:
Acknowledge
Figure 9. I
2
C-bus Control I/F Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4527BVQ | HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC |
| AK4528 | HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC |
| AK4528VF | HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC |
| AK4529 | High Performance Multi-channel Audio CODEC |
| AK4532 | Internet/Network/General Purpose Multimedia Audio CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4527BVQ | 制造商:AKM 制造商全稱:AKM 功能描述:HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC |
| AK4528 | 制造商:AKM 制造商全稱:AKM 功能描述:HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC |
| AK4528_04 | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance 24Bit 96kHz Audio CODEC |
| AK4528_12 | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance 24Bit 96kHz Audio CODEC |
| AK4528VF | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance 24Bit 96kHz Audio CODEC |
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