
ASAHI KASEI
[AK4524]
M0050-E-01
1999/5
- 27 -
+
4.75
~
5.25V
Analog Supply
10u
10u
0.1u
0.1u
0.1u
0.1u
5
Rch Out
Lch Out
2.7
~
5.25V
Digital Supply
Mode
Setting
Audio
Controller
Rch
LPF
Lch
LPF
VCOM
AINR
AINL
VREF
AGND
VA
XTO
XTI
XTALE
LRCK
BICK
SDTO
SDTI
CDTI
CCLK
CS
CIF
CLKO
VT
VD
DGND
AOUTL-
AOUTL+
AOUTR-
AOUTR+
PD
M/ S
1
2
3
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
21
24
25
26
27
28
AK4524
TEST
+
10
22
23
4
Figure 11. Typical Connection Diagram (EXT clock mode)
1. Grounding and Power Supply Decoupling
The AK4524 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied
from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is taken care.
VT is a power supply pin to interface with the external ICs and is supplied from digital supply in system. AGND and
DGND of the AK4524 should be connected to analog ground plane. System analog ground and digital ground should be
connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be
as near to the AK4524 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference
The differential voltage between VREF and AGND sets the analog input/output range. VREF pin is normally connected to
VA with a 0.1uF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10uF parallel with a
0.1uF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be
drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to
avoid unwanted coupling into the AK4524.