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參數資料
| 型號： | AK4524 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 24BIT 96KHZ AUDIO CODEC |
| 中文描述： | 24位96kHz的音頻編解碼器 |
| 文件頁數： | 20/31頁 |
| 文件大?。?/td> | 320K |
| 代理商： | AK4524 |
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ASAHI KASEI
[AK4524]
M0050-E-01
1999/5
- 20 -
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Control Register Setup Sequence
When PD pin goes “L” to “H” upon power-up etc., the AK4524 should operate by the next sequence. In this case, all
control registers are set to initial values and the AK4524 is in the reset state.
(1)
Set the clock mode and the audio data interface mode.
(2)
Cancel the reset state by setting RSTAD or RSTDA to “1”. Refer to Reset Contorl Register (01H).
(3)
ADC outputs and DAC outputs should be muted externally until cancelling each reset state. In master mode, there is
a possibility the frequency and duty of LRCK and BICK outputs become an abnormal state.
The clock mode should be changed after setting RSTAD and RSTDA to “0”. At that time, ADC outputs and DAC outputs
should be muted externally. In master mode, there is a possibility the frequency and duty of LRCK and BICK outputs
become an abnormal state.
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Register Definitions
Addr
00H
Register Name
Power Down Control
RESET
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
D1
D0
PWVR
1
PWAD
1
PWDA
1
PWDA: DAC power down
0: Power down
1: Power up
Only DAC section is powered down by “0” and then the AOUTs go Hi-Z immediately. The OATTs also go
“00H”. But the contents of all register are not initialized and enabled to write to the registers. After exiting
the power down mode, the OATTs fade in the setting value of the control register (06H & 07H). The analog
outputs should be muted externally as some pop noise may occur when entering to and exiting from this
mode.
PWAD: ADC power down
0: Power down
1: Power up
Only ADC section is powered down by “0” and then the SDTO goes “L” immediately. The IPGAs also go
“00H”. But the contents of all register are not initialized and enabled to write to the registers. After exiting
the power down mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time,
ADCs output “0” during first 516 LRCK cycles.
PWVR: Vref power down
0: Power down
1: Power up
All sections are powered down by “0” and then both ADC and DAC do not operate. The contents of all
register are not initialized and enabled to write to the registers. When PWAD and PWDA go “0” and PWVR
goes “1”, only VREF section can be powered up.
相關PDF資料 |
PDF描述 |
|---|---|
| AK4524VF | 24BIT 96KHZ AUDIO CODEC |
| AK4525 | 20BIT STEREO ADC & DAC WITH X TAL OSC |
| AK4525VF | 20BIT STEREO ADC & DAC WITH X TAL OSC |
| AKD4525 | 20BIT STEREO ADC & DAC WITH X TAL OSC |
| AK4527B | HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AK4524_04 | 制造商:AKM 制造商全稱:AKM 功能描述:24Bit 96kHz Audio CODEC |
| AK4524_12 | 制造商:AKM 制造商全稱:AKM 功能描述:24Bit 96kHz Audio CODEC |
| AK4524VF | 制造商:AKM 制造商全稱:AKM 功能描述:24Bit 96kHz Audio CODEC |
| AK4524VFP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:RECOM REPLC AK4620BVF |
| AK4524VM | 制造商:AKM 制造商全稱:AKM 功能描述:24Bit 96kHz Audio CODEC |
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