參數(shù)資料
型號(hào)： AK4524
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： 24BIT 96KHZ AUDIO CODEC
中文描述： 24位96kHz的音頻編解碼器
文件頁(yè)數(shù)： 22/31頁(yè)
文件大?。?/td> 320K
代理商： AK4524
ASAHI KASEI
[AK4524]
M0050-E-01
1999/5
- 22 -
Addr
03H
Register Name
Deem and Volume Control
RESET
D7
D6
0
0
D5
0
0
D4
ZCEI
1
D3
D2
D1
D0
SMUTE
0
ZTM1
1
ZTM0
0
DEM1
0
DEM0
1
DEM1-0: De-emphasis response (see Table 7)
00: 44.1kHz
01: OFF
10: 48kHz
11: 32kHz
Initial: OFF
ZTM1-0: Zero crossing time out period select (see Table 6)
Initial: 1024fs
ZCEI: ADC IPGA Zero crossing enable
0: Input PGA gain changes occur immediately
1: Input PGA gain changes occur only on zero-crossing or after timeout.
Initial: 1 (Enable)
SMUTE: DAC Input Soft Mute control
0: Normal operation
1: DAC outputs soft-muted
The soft mute is independent of the output ATT and performed digitally.
Addr
04H
05H
Register Name
Lch IPGA Control
Rch IPGA Control
RESET
D7
D6
D5
D4
D3
D2
D1
D0
IPGL7
IPGR7
0
IPGL6
IPGR6
1
IPGL5
IPGR5
1
IPGL4
IPGR4
1
IPGL3
IPGR3
1
IPGL2
IPGR2
1
IPGL1
IPGR1
1
IPGL0
IPGR0
1
IPGL/R7-0: ADC Input Gain Level
Refer to Table 10
Initial: 7FH (0dB)
Digital ATT with 128 levels operates when writing data of less than 7FH. This ATT is a linear ATT with
8032 levels internally and these levels are assigned to pseudo-log data with 128 levels. The transition
between ATT values has 8032 levels and is done by soft changes. For example, when ATT changes from
127 to 126, the internal ATT value decreases from 8031 to 7775 one by one every fs cycles. It takes 8031
cycles (182ms@fs=44.1kHz) from 127 to 0 (Mute).
The IPGAs are set to “00H” when PD pin goes “L”. After returning to “H”, the IPGAs fade in the initial
value, “7FH” by 8031 cycles.
The IPGAs are set to “00H” when PWAD goes “0”. After returning to “1”, the IPGAs fade in the current
value. But the ADCs output “0” during first 516 cycles.
The IPAGs are set to “00H” when RSTAD goes “0”. After returning to “1”, the IPGAs fade in the current
value. But the ADCs output “0” during first 516 cycles.
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