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參數(shù)資料
| 型號： | AK4395 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | ADVANCED MULTI-BIT 192KHZ 24-BIT DAC |
| 中文描述： | 先進(jìn)的多位192kHz的24位DAC |
| 文件頁數(shù)： | 11/26頁 |
| 文件大?。?/td> | 277K |
| 代理商： | AK4395 |
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ASAHI KASEI
[AK4395]
MS0040-E-00
2000/7
- 11 -
OPERATION OVERVIEW
n
System
Clock
The external clocks, which are required to operate the AK4395, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). CKS0/1/2 set the frequency of MCLK at each sampling
speed (Table 2). In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 6),
and the internal master clock becomes the appropriate frequency, it is not necessary to set DFS0/1 and CKS0/1/2. In
parallel mode, CKS2 and DFS1 are fixed to “0”.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4395 is in normal operation
mode (PD = “H”). If these clocks are not provided, the AK4395 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4395 should be in the power-down mode
(PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4395 is in power-down mode
until MCLK and LRCK are input.
DFS1
0
0
1
DFS0
0
1
0
Sampling Rate (fs)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
30kHz~54kHz
60kHz~108kHz
120kHz~216kHz
Default
Table 1. Sampling Speed (Manual Setting Mode)
Mode
0
1
2
3
4
5
6
7
CKS2
0
0
0
0
1
1
1
1
CKS1
0
0
1
1
0
0
1
1
CKS0
0
1
0
1
0
1
0
1
Normal
256fs
256fs
384fs
384fs
512fs
512fs
768fs
768fs
Double
128fs
256fs
192fs
384fs
256fs
N/A
384fs
N/A
Quad
N/A
N/A
N/A
N/A
128fs
N/A
192fs
N/A
Default
Table 2. System Clocks (Manual Setting Mode)
Note: The master clock at quad speed supports only 128fs or 192fs.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK
BICK
64fs
256fs
384fs
512fs
768fs
8.1920MHz
11.2896MHz
12.2880MHz
12.2880MHz
16.9344MHz
18.4320MHz
16.3840MHz
22.5792MHz
24.5760MHz
24.5760MHz
33.8688MHz
36.8640MHz
2.0480MHz
2.8224MHz
3.0720MHz
Table 3. System clock example (Normal Speed Mode @Manual Setting Mode)
相關(guān)PDF資料 |
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| AK4395VF | ADVANCED MULTI-BIT 192KHZ 24-BIT DAC |
| AK4396 | Advanced Multi-Bit 192kHz 24-Bit ツヒ DAC |
| AK4396VF | Advanced Multi-Bit 192kHz 24-Bit ツヒ DAC |
| AK4397 | High Performance Premium 32-Bit DAC |
| AK4397EQ | High Performance Premium 32-Bit DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4395VF | 制造商:AKM 制造商全稱:AKM 功能描述:ADVANCED MULTI-BIT 192KHZ 24-BIT DAC |
| AK4395VF-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4395VFP | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:ADVANCED MULTI-BIT 192KHZ 24-BIT DAC |
| AK4395VFP-E2 | 功能描述:IC DAC 24BIT STEREO 28VSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| AK4396 | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz sampling 24Bit ツヒ DAC |
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