
ASAHI KASEI
[AK4394]
M0081-E-00
1999/11
- 8 -
DC CHARACTERISTICS
(Ta = 25
°
C; AVDD, DVDD = 4.75~5.25V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout = -100
m
A)
Low-Level Output Voltage (Iout = 100
m
A)
Input Leakage Current (Note 17)
Note: 17. DFS0, P/S pins have internal pull-down or pull-up devices, nominally 100k
W
.
Symbol
VIH
VIL
VOH
VOL
Iin
min
2.2
-
typ
-
-
-
-
-
max
-
0.8
-
0.5
±
10
Units
V
V
V
V
μA
DVDD-0.5
-
-
SWITCHING CHARACTERISTICS
(Ta = 25
°
C; AVDD, DVDD = 4.75~5.25V; C
L
= 20pF)
Parameter
Master Clock Timing
Frequency
Duty Cycle
LRCK Frequency
(Note 18)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
Serial Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “
-
” to LRCK Edge (Note 19)
LRCK Edge to BICK “
-
” (Note 19)
SDATA Hold Time
SDATA Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “
ˉ
” to CCLK “
-
”
CCLK “
-
” to CSN “
-
”
Reset Timing
PDN Pulse Width (Note 20)
Symbol
min
typ
max
Units
fCLK
dCLK
7.7
40
41.472
60
MHz
%
fsn
fsd
fsq
Duty
30
60
120
45
54
108
216
55
kHz
kHz
kHz
%
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fs
1/64fs
1/64fs
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
tPD
150
ns
Notes: 18. When the normal/double/quad speed modes are switched, AK4394 should be reset by PDN pin or RSTN bit.
19. BICK rising edge must not occur at the same time as LRCK edge.
20. The AK4394 can be reset by bringing PDN “L” to “H”.
When the states of CKS2-0 or DFS1-0 change, the AK4394 should be reset by PDN pin or RSTN bit.