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參數資料
| 型號： | AK4394 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | ADVANCED MULTI-BIT 192KHZ 24-BIT DAC |
| 中文描述： | 先進的多位192kHz的24位DAC |
| 文件頁數： | 18/26頁 |
| 文件大?。?/td> | 299K |
| 代理商： | AK4394 |
ASAHI KASEI
[AK4394]
M0081-E-00
1999/11
- 18 -
n
Mode Control Interface
Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4394. For DIF0/1/2,
CKS1 and DFS0, the setting of pin and register are “ORed” internally. So, even serial control mode, these functions can be
also controlled by pin setting.
The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting must be all “L”. Internal registers may
be written by 3-wire μP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2bits,
C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first,
8bits). The AK4394 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge. The
writing of data becomes valid by CSN “
-
”. The clock speed of CCLK is 5MHz(max). The CSN and CCLK must be fixed
to “H” when the register does not be accessed.
Function
Double speed
Quad speed
De-emphasis
SMUTE
Zero Detection
Slow roll-off response
Parallel mode
O
X
O
O
X
X
Serial mode
O
O
O
O
O
O
Table 8. Function List (O: Available, X: Not available)
PDN = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4394 should be reset by PDN = “L”.
In serial mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized.
CDTI
CCLK
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CSN
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 8. Control I/F Timing
*The AK4394 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4394 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register
is inhibited.
*
For setting the registers, the following sequence is recommended.
Control 1 register
(1) Writing RSTN = “0” and other bits (D6-D1) to the register at the same time.
(2) Writing RSTN = “1” to the register. The other bits are no change.
Control 2 register
This writing sequence has no limitation like control 1 register.
When setting DEM0/1 and SMUTE, RSTN is not needed.
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