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參數(shù)資料
| 型號： | AK4387ET |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 106dB 192kHz 24-Bit 2ch ツヒ DAC |
| 中文描述： | 一零六分貝192kHz的24位2通道ツヒ數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 257K |
| 代理商： | AK4387ET |
ASAHI KASEI
[AK4387]
MS0429-E-00
2005/09
- 12 -
Zero Detection
The AK4387 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input
data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin
of both channels go to “L” at 2~3/fs after RSTN bit returns to “1”. Zero detect function can be disabled by DZFE bit. In
this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF pin.
Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by
-
∞
during ATT_DATA
×
ATT transition time (Table 9) from the current ATT level. When the SMUTE bit is returned to
“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA
×
ATT
transition time. If the soft mute is cancelled before attenuating to -
∞
after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE bit
Attenuation
DZF pin
ATT Level
-
∞
AOUT
8192/fs
GD
(2)
GD
(1)
(3)
(4)
(1)
Notes:
(1) ATT_DATA
×
ATT transition time (Table 9). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -
∞
after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft Mute and Zero Detection
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| AK4388AETP-E2 | 功能描述:IC DAC 24BIT PARALLEL 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AK4388ET | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz 24-Bit 2ch ツヒ DAC |
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