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參數(shù)資料
| 型號： | AK4386 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 100DB 96KHZ 24 BIT 2CH |
| 中文描述： | 100dB的96kHz的24位二通 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 129K |
| 代理商： | AK4386 |
ASAHI KASEI
[AK4386]
MS0280-E-00
2003/12
- 9 -
OPERATION OVERVIEW
n
System Clock
The external clocks, which are required to operate the AK4386, are MCLK, BICK and LRCK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. The MCLK frequency is detected from the relation between MCLK and LRCK
automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 pins (Table 1).
The sampling speed mode is set depending on the MCLK frequency automatically for Auto mode (DFS1 pin = DFS0 pin
= “H”) (Table 2).
The AK4386 is automatically placed in the power save mode when MCLK stops in the normal operation mode (PDN pin
= “H”), and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4386 is powered up. After
exiting reset at power-up etc., the AK4386 is in the power-down mode until MCLK and LRCK are input.
When the states of DIF1-0 pins change in the normal operation mode, the AK4386 should be reset by PDN pin.
Mode
DFS1
DFS0
Normal Speed
L
L
Double Speed
L
H
Half Speed
H
L
Auto
H
H
Table 1. System Clock Example
MCLK Frequency
Sampling Speed Mode
512/768fs
Normal Speed
128/192/256/384fs
Double Speed
1024/1536fs
Half Speed
Table 2. Auto Mode
n
Audio Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 pins as shown in Table 3 can select four
serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of
BICK. Mode 3 can be used for 16bit I
2
S Compatible format by zeroing the unused LSBs at BICK
≥
48fs or BICK = 32fs.
Mode
DIF1
DIF0
0
L
L
16bit, LSB justified
1
L
H
24bit, LSB justified
2
H
L
24bit, MSB justified
3
H
H
16/24bit, I
2
S Compatible
Table 3. Audio Interface Format
fs
MCLK Frequency
256/384/512/768fs
128/192/256/384fs
512/768/1024/1536fs
Table 2
8
～
48kHz
48
～
96kHz
8
～
24kHz
8
～
96kHz
fs
8
～
48kHz
48
～
96kHz
8
～
24kHz
SDTI Format
BICK
≥
32fs
≥
48fs
≥
48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
≥
48fs or 32fs
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| AK4386VT | 100DB 96KHZ 24 BIT 2CH |
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| AK4386ET | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit 2ch ???￡ DAC |
| AK4386ETP-E2 | 功能描述:IC DAC 24BIT STEREO 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AK4386VT | 制造商:AKM 制造商全稱:AKM 功能描述:100DB 96KHZ 24 BIT 2CH |
| AK4386VTP-E2 | 制造商:AKM Semiconductor Inc 功能描述:AK4386VTP-E2 |
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