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參數(shù)資料
| 型號： | AK4386 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 100DB 96KHZ 24 BIT 2CH |
| 中文描述： | 100dB的96kHz的24位二通 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 129K |
| 代理商： | AK4386 |
ASAHI KASEI
[AK4386]
MS0280-E-00
2003/12
- 13 -
(2) Power save by MCLK stop (PDN pin = “H”)
PDN pin
Normal Operation
Internal
State
Power-save
Normal Operation
GD
GD
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, BICK, LRCK
(2)
(3)
External
MUTE
(5)
VCOM
(2)
MCLK Stop
Power-down
Power-down
(4)
(4)
(4)
Hi-Z
(6)
(6)
(5)
(1)
Notes:
(1) PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7
μ
F is attached between VCOM pin and
VSS.)
(2) The analog output corresponding to digital input has the group delay (GD).
(3) The digital data can be stopped. The click noise after MCLK is input again by inputting the “0” data to this section
can be reduced.
(4) Click noise occurs in 3
～
4LRCK at both edges (
↑
↓
) of PDN signal, MCLK inputs and MCLK stops. This noise is
output even if “0” data is input.
(5) The external clocks (BICK and LRCK) can be stopped in the power down mode (MCLK stop).
(6) Please mute the analog output externally if the click noise (4) influences system application. The timing example
is shown in this figure.
Figure 6. Power-down/up sequence example 2
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