
ASAHI KASEI
[AK4380]
MS0018-E-01
2000/8
- 2 -
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Ordering Guide
AK4380VT
AKD4380
-40
~
+85
°
C
Evaluation Board for AK4380
16pin TSSOP (0.65mm pitch)
n
Pin Layout
1
MCLK
LRCK
BICK
SMUTE/CSN
DFS/CCLK
DIF0/CDTI
Top
View
2
3
4
5
6
7
8
DZF
VREF
VSS
VDD
VCOM
AOUTL
AOUTR
P/S
16
15
14
13
12
11
10
9
PDN
SDTI
PIN/FUNCTION
No.
1
Pin Name
MCLK
I/O
I
Function
Master Clock Input Pin
An external TTL clock should be input on this pin.
Audio Serial Data Clock Pin
Audio Serial Data Input Pin
L/R Clock Pin
Power-Down Mode Pin
When at “L”, the AK4380 is in the power-down mode and is held in reset.
The AK4380 should always be reset upon power-up.
Soft Mute Pin in parallel mode
“H”: Enable, “L”: Disable
Chip Select Pin in serial mode
Double Speed Sampling Mode Pin in parallel mode
“L”: Normal Speed, “H”: Double Speed
Control Data Input Pin in serial mode
Audio Data Interface Format Pin in parallel mode
Control Data Input Pin in serial mode
Parallel/Serial Select Pin (Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
Rch Analog Output Pin
Lch Analog Output Pin
Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1
μ
F ceramic capacitor in parallel with
a 10
μ
F electrolytic cap.
Ground Pin
Power Supply Pin
Voltage Reference Input Pin
Data Zero Input Detect Pin
When SDTI of both channels follow a total 8192 LRCK cycles with “0” input
data, this spin goes to “H”.
2
3
4
5
BICK
SDTI
LRCK
PDN
I
I
I
I
SMUTE
I
6
CSN
DFS
I
I
7
CCLK
DIF0
CDTI
P/S
I
I
I
I
8
9
10
11
12
AOUTR
AOUTL
VCOM
O
O
O
13
14
15
16
VSS
VDD
VREF
DZF
-
-
I
O
Note: All input pins except pull-up pin should not be left floating.