參數(shù)資料
型號(hào)： AK4380VT
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 100dB 24BIT 96kHz 2CH DAC
中文描述： 100dB的24位96kHz的2聲道數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 14/21頁(yè)
文件大?。?/td> 226K
代理商： AK4380VT
ASAHI KASEI
[AK4380]
MS0018-E-01
2000/8
- 14 -
n
System Reset
The AK4380 should be reset once by bringing PDN = “L” upon power-up. The AK4380 is powered up and the internal
timing starts clocking by LRCK “
↑
” after exiting reset and power down state by MCLK. The AK4380 is in the power-down
mode until MCLK and LRCK are input.
n
Power-down
The AK4380 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure
6 shows an example of the system timing at the power-down and power-up.
Normal Operation
Internal
State
PDN
Power-down
Normal Operation
GD
GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, LRCK, BICK
(1)
(3)
(6)
DZF
External
MUTE
(5)
(3)
(1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1)
The analog output corresponding to the digital input has a group delay, GD.
(2) Analog outputs are floating (Hi-Z) at the power-down mode.
(3) Click noise occures at the edges(“
↑
↓
”) of PDN signal. This noise is output even if input data is “0”.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise(3) influences system application. The timing example is
shown in this figure.
(6) DZF pin is “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up sequence example
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參數(shù)描述
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