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參數(shù)資料
| 型號(hào)： | AK4363 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 96KHz 24 Bit ΔΣ DAC with PLL(帶鎖相環(huán)的采樣速度96KHz，24位立體聲 ΔΣ D/A轉(zhuǎn)換器) |
| 中文描述： | 96KHz的24位ΔΣDAC，具有鎖相環(huán)（帶鎖相環(huán)的采樣速度96KHz的24位立體聲ΔΣ的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 21/29頁 |
| 文件大?。?/td> | 248K |
| 代理商： | AK4363 |
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ASAHI KASEI
[AK4363]
MS0015-E-01
2000/07
- 21 -
n
Serial Control Interface
The AK4363 can control its functions via registers. Internal registers may be written by 2 types of control mode. The chip
address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default
values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be
initialized.
(1) 3-wire Serial Control Mode (I2C = “L”)
Internal registers may be written to the 3 wire μP interface pins (CSN,CCLK and CDTI). The data on this interface
consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to “1”; Write only), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock
speed of CCLK is 5MHz(max). The CSN and CCLK pins should be held to “H” except for access.
CDTI
CCLK
CSN
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
C1-C0:Chip Address (C1=CAD1, C0=CAD0)
R/W:
Read/Write (Fixed to “1” : Write only)
A4-A0: Register Address
D7-D0:Control Data
(2) I
2
C Bus Control Mode (I2C = “H”)
Internal registers may be written to I
2
C Bus interface pins: SCL & SDA. The data on this interface consists of Chip
address (2bits, CAD0/1), Read/Write (1bit, Fixed to “0”; Write only), Register address (MSB first, 5bits) and
Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of SCL and data is clocked out on
the falling edge. Data can be written after a high-to-low transition of SDA when SCL is “H”(start condition), and is
latched after a low-to-high transition of SDA when SCL is “H”(stop condition). The clock speed of SCL is
100kHz(max). The CSN pin should be connected to DVDD at I
2
C Bus control mode. The AK4363 does not have a
register address auto increment capability.
SCL
SDA
0
0
1
0
0
R/W
Start
Stop
ACK
ACK
ACK
C1 C0
0
0
0 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:Chip Address (C1=CAD1, C0=CAD0)
R/W:
Read/Write (Fixed to “0” : Write only)
A4-A0: Register Address
D7-D0:Control Data
ACK:
Acknowledge
* When the AK4363 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
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| AK4364096G | 制造商:ACCUTEK 制造商全稱:ACCUTEK MICROCIRCUIT CORPORATION 功能描述:65,536 x 32 Bit CMOS/BiCMOS Static Random Access Memory |
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