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參數(shù)資料
| 型號： | AK4363 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 96KHz 24 Bit ΔΣ DAC with PLL(帶鎖相環(huán)的采樣速度96KHz，24位立體聲 ΔΣ D/A轉(zhuǎn)換器) |
| 中文描述： | 96KHz的24位ΔΣDAC，具有鎖相環(huán)（帶鎖相環(huán)的采樣速度96KHz的24位立體聲ΔΣ的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 248K |
| 代理商： | AK4363 |
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ASAHI KASEI
[AK4363]
MS0015-E-01
2000/07
- 14 -
OPERATION OVERVIEW
n
System Clock Input
1) PLL mode (EXT = “0”)
A fully integrated analog phase locked loop generates MCKO which is locked to the 27MHz reference input. The
frequency of the MCKO output is selectable via register data of CKS2-0, DFS1-0 and FS1-0 as defined in Table 1-3.
The PLL requires 20ms lock time whenever MCKO frequency selection changes or MCKO source changes from EXT
mode to PLL mode, but 100ms upon power-up after 27MHz system clock stabilizes. Serial input data is zeroed internally
while PLL is unlocked to prevent spurious output. When 27MHz clock is not present, the internal VCO frequency is
pulled to its minimum value.
The LRCK input must be synchronous with MCKO, however the phase is not critical. Internal timing is synchronized to
LRCK input upon power-up.
When MCKO frequency changes by register data of CKS2-0, DFS1-0 or FS1-0 during normal operation, the AK4363
should be reset by PDN pin “L” or RSTN bit “0”. Serial input data is zeroed internally until PLL is locked after exiting
resetting.
2) External mode (EXT = “1”)
When EXT bit is set to “1”, master clock can be input via MCKI pin. In this case, MCKO frequency is same as MCKI and
it is not necessary to change the register data of FS1-0. The external clocks which are required to operate the AK4363 are
MCKI, LRCK and BICK. The master clock (MCKI) should be synchronized with sampling clock (LRCK) but the phase
is not critical. MCKI is used to operate the digital interpolation filter and the delta-sigma modulator. The frequency of
MCKI can be set by CKS2-0, and can be selected to half, normal or double speed mode by DFS1-0 (See Table 2).
In this case, internal VCO is powered down. Therefore, all external clocks should always be present whenever the
AK4363 is in the normal operation mode (PDN = “H”). If these clock are not provided, the AK4363 may draw excess
current and may not possibly operate properly because the device utilizes dynamic refreshed logic internally. If the
external clocks are not present, the AK4363 should be in the power-down mode (PDN = “L”) or in the reset mode (RSTN
= “0”). After exiting reset at power-up etc., the AK4363 is in the power-down mode until MCKI and LRCK are input.
When the register data of CKS2-0 or DFS1-0 is changed during normal operation, the AK4363 should be reset by PDN
pin “L” or RSTN bit “0”.
DFS1-0
“00”
(Normal speed)
32
44.1
48
FS1
FS0
“11
(Half speed)
16
22.05
24
“01”
(Double speed)
64
88.2
96
1
0
0
0
0
1
default (DFS1-0 = “00”)
Table 1. Sampling Frequency [kHz] (FS1-0 = “11”, DFS1-0 = “10”: reserved)
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