參數(shù)資料
型號(hào)： AK4363
廠(chǎng)商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 96KHz 24 Bit ΔΣ DAC with PLL(帶鎖相環(huán)的采樣速度96KHz，24位立體聲 ΔΣ D/A轉(zhuǎn)換器)
中文描述： 96KHz的24位ΔΣDAC，具有鎖相環(huán)（帶鎖相環(huán)的采樣速度96KHz的24位立體聲ΔΣ的D / A轉(zhuǎn)換器）
文件頁(yè)數(shù)： 19/29頁(yè)
文件大小： 248K
代理商： AK4363
ASAHI KASEI
[AK4363]
MS0015-E-01
2000/07
- 19 -
n
Power-down
The DAC is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same time.
The internal register values are initialized by PDN “L”. This reset should always be done after power-up. Because some
click noise occurs at the edge of PDN, the analog output should be muted externally if the click noise influences system
application.
Normal Operation
Internal
State
PDN
Power-down
Normal Operation
GD
GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCKI, LRCK, BICK
(1)
(3)
(6)
DZF
External
MUTE
(5)
(3)
(1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCKI, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pin is “L” in the power-down mode (PDN = “L”).
Figure 7. Power-down/up sequence example
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