
ASAHI KASEI
[AK4359]
MS0289-E-00
2004/02
- 14 -
Audio Serial Interface Format
In parallel mode, the DIF0-1 pins as shown in Table 7 can select four serial data modes. In serial mode, the DIF0-2 bits
s shown in Table 8 can select five serial data modes. Initial value of DIF0-2 bits is “010”. In all modes the serial data is
MSB-first, 2’s complement format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified
formats by zeroing the unused LSBs.
In serial mode, when TDM0 bit = “1”, the audio interface becomes TDM mode. In TDM256 mode (TDM1 bit = “0”,
Table 9), the serial data of all DAC (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins is ignored.
BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be 1/256fs at least. The serial data is MSB-first,
2’s complement format. The input data to SDTI1 pin is latched on the rising edge of BICK. In TDM128 mode (TDM1 bit
= “1”, Table 10), the serial data of DAC (four channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other four data (L3,
R3, L4, R4) is input to the SDTI2. The input data to SDTI3-4 pins is ignored. BICK should be fixed to 128fs.
Mode
DIF1
DIF0
SDTI Format
0
0
0
16bit LSB Justified
1
0
1
20bit LSB Justified
2
1
0
24bit MSB Justified
3
1
1
24bit I
2
S Compatible
LRCK
H/L
H/L
H/L
L/H
BICK
≥
32fs
≥
40fs
≥
48fs
≥
48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Table 7. Audio Data Formats (Parallel mode)
Mode
0
1
2
3
4
TDM1
0
0
0
0
0
TDM0
0
0
0
0
0
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTI Format
16bit LSB Justified
20bit LSB Justified
24bit MSB Justified
24bit I
2
S Compatible
24bit LSB Justified
LRCK
H/L
H/L
H/L
L/H
H/L
BICK
≥
32fs
≥
40fs
≥
48fs
≥
48fs
≥
48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Default
Table 8. Audio Data Formats (Serial mode)
SDTI
Mode 0
BICK
(32fs)
LRCK
SDTI
Mode 0
15
14
6
5
4
BICK
(64fs)
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
3
2
1
0
15
14
0
14
1
15
16
17
31
0
1
14
15
16
17
31
0
1
15
14
0
15
14
0
Don’t care
Don’t care
15:MSB, 0:LSB
15
14
6
5
4
3
2
1
0
Lch Data
Rch Data
Figure 1. Mode 0 Timing