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參數(shù)資料
| 型號(hào)： | AK4357 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192kHz 24-Bit 6ch DAC with DSD Input |
| 中文描述： | 192kHz的24位6通道DAC，具有DSD輸入 |
| 文件頁數(shù)： | 15/27頁 |
| 文件大?。?/td> | 195K |
| 代理商： | AK4357 |
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ASAHI KASEI
[AK4357]
MS0088-E-02
2002/07
- 15 -
n
Zero Detection
When the input data at all channels are continuously zeros for 8192 LRCK cycles, The AK4357 has Zero Detection like Table
13. DZF pin immediately goes to “L” if input data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF
pin goes to “H”. DZF pin goes to “L” at 4~5LRCK if input data of each channel is not zero after RSTN bit returns to “1”. Zero
detect function can be disabled by DZFE bit. In this case, DZF pins of both channels are always “ L”. DZFB bit can invert the
polarity of DZF pin. When one of PW1-3 bit is set to “0”, the input data of DAC which the PW bit is set to ”0” should be zero
in order to enable zero detection of the other channels . When all PW1-3 bits are set to “0”, DZF pin fixes “L”. When DZFM
bit set to “1”, only the input data at all channels are continuously zeros for 8192 LRCK cycles, all DZF pins go to “H”.
DZF Pin
DZFL1
When Lch Data of DAC1 is “0”, DZFL1 pin goes “H”.
DZFR1
When Rch Data of DAC1 is “0”, DZFR1 pin goes “H”.
DZF23
When all Lch and Rch Data of DAC2,3 are “0”, DZF23 goes “H”.
Table 13. DZF pin Operations
n
Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by -
∞
during ATT_DATA
×
ATT transition time (Table 12) from the current ATT level. When the SMUTE bit is returned to 0”, the
mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA
×
ATT transition time.
If the soft mute is cancelled before attenuating to -
∞
after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the
signal transmission.
Operations
SMUTE bit
Attenuation
DZF pin
ATT Level
-
∞
AOUT
8192/fs
GD
(2)
GD
(1)
(3)
(4)
(1)
Notes:
(1) ATT_DATA
×
ATT transition time (Table 12). For example, in Normal Speed Mode, this time is 1792LRCK cycles
(1792/fs) at ATT_DATA=128.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -
∞
after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 6. Soft Mute and Zero Detection
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| AK4358VQP-L | 功能描述:IC DAC 24BIT SERIAL 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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