參數(shù)資料
型號(hào)： AK4342
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 24-Bit Stereo DAC with HP-AMP & 2V Line-Out
中文描述： 24位立體聲DAC惠普腺苷
文件頁(yè)數(shù)： 31/43頁(yè)
文件大?。?/td> 580K
代理商： AK4342
ASAHI KASEI
[AK4342]
MS0506-E-02
2006/07
- 31 -
2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4342. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 09H prior to generating a stop condition, the address
counter will “roll over” to 00H and the previous data will be overwritten.
The AK4342 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
2-1. CURRENT ADDRESS READ
The AK4342 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4342 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition,
the AK4342 ceases transmission.
SDA
Slave
Address
S
S
T
A
R
T
R/W="1"
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
S
T
O
P
Data(n)
Figure 26. CURRENT ADDRESS READ
2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4342 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but instead generates a stop condition, the AK4342 ceases transmission.
SDA
Slave
Address
S
S
T
A
R
T
R/W="0"
A
C
K
A
C
K
A
C
K
Data(n)
A
C
K
Data(n+x)
A
C
K
P
S
T
O
P
Sub
Address(n)
S
Slave
Address
R/W="1"
S
T
A
R
T
Data(n+1)
A
C
K
A
C
K
Figure 27. RANDOM ADDRESS READ
相關(guān)PDF資料
PDF描述
AK4342EN 24-Bit Stereo DAC with HP-AMP & 2V Line-Out
AK4343 Stereo DAC with HP/RCV/SPK-AMP
AK4343EN Stereo DAC with HP/RCV/SPK-AMP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4342EN 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit Stereo DAC with HP-AMP & 2V Line-Out
AK4342EN-L 制造商:ASAHI 功能描述:
AK4342ENP-L 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:
AK4343 制造商:AKM 制造商全稱:AKM 功能描述:Stereo DAC with built-in HP/RCV/SPK amplifier
AK434-3 功能描述:CABLE CENTRONICS F-F 3M RoHS:否 類別:電纜組件 >> D形，Centronics 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 配置:VHDCI 68 位置公型至公型 長(zhǎng)度:10.00'（3.05m） 纜線類型:圓形 - 黑色 屏蔽:屏蔽 樣式:SCSI Ultra 2
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