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參數(shù)資料
| 型號： | AK4342 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 24-Bit Stereo DAC with HP-AMP & 2V Line-Out |
| 中文描述： | 24位立體聲DAC惠普腺苷 |
| 文件頁數(shù)： | 17/43頁 |
| 文件大?。?/td> | 580K |
| 代理商： | AK4342 |
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ASAHI KASEI
[AK4342]
MS0506-E-02
2006/07
- 17 -
Serial Data Interface
The AK4342 interfaces with external system via the SDATA, BICK and LRCK pins. Five data formats are supported and
are selected by the DIF2, DIF1 and DIF0 bits (Table 4). Mode 0 is compatible with existing 16bit DACs and digital filters.
Mode 1 is a 20bit version of Mode 0. Mode 4 is a 24bit version of Mode 0. Mode 2 is similar to AKM ADCs and many
DSP serial ports. Mode 3 is compatible with the I
2
S serial data protocol. In Modes 2 and 3 with BICK
≥
48fs, the following
formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four zeros (21st
to 24th bits). In all modes, the serial data is MSB first and 2’s complement format. The polarity of BICK can be inverted
by the BCKP bit, the polarity of LRCK can be inverted by the LRP bit. PMDAC bit should be set to “0” when BCKP or
LRP bits are changed.
DIF2
bit
bit
bit
32fs
≤
BICK
≤
128fs (Half/Normal Speed Mode)
32fs
≤
BICK
≤
64fs (Double Speed Mode)
40fs
≤
BICK
≤
128fs (Half/Normal Speed Mode)
40fs
≤
BICK
≤
64fs (Double Speed Mode)
48fs
≤
BICK
≤
128fs (Half/Normal Speed Mode)
48fs
≤
BICK
≤
64fs (Double Speed Mode)
BICK=32fs (Half/Normal/Double Speed Mode)
or
48fs
≤
BICK
≤
128fs (Half/Normal Speed Mode)
48fs
≤
BICK
≤
64fs (Double Speed Mode)
48fs
≤
BICK
≤
128fs (Half/Normal Speed Mode)
48fs
≤
BICK
≤
64fs (Double Speed Mode)
Table 4. Audio Data Format
LRCK Polarity
BCPKP bit
LRP bit
Lch Data
H: Mode 0,1,2,4
L: Mode 3
H: Mode 3
L: Mode 0,1,2,4
H: Mode 3
L: Mode 3
H: Mode 0,1,2,4
L: Mode 3
H: Mode 3
L: Mode 0,1,2,4
H: Mode 3
L: Mode 3
Table 5. LRCK and BICK Polarities
LRCK
DIF1
DIF0
MODE
BICK
Figure
0
0
0
0: 16bit, LSB justified
Figure 12
0
0
1
1: 20bit, LSB justified
Figure 13
0
1
0
2: 24bit, MSB justified
Figure 14
Default
0
1
1
3: I
2
S Compatible
Figure 15
1
0
0
4: 24bit, LSB justified
Figure 13
Rch Data
BICK Polarity
(SDATA Latch Timing)
0
0
L: Mode 0,1,2,4
↑
Default
0
1
H: Mode 0,1,2,4
↑
1
0
L: Mode 0,1,2,4
↓
1
1
H: Mode 0,1,2,4
↓
SDATA
Mode 0
BICK
(32fs)
SDATA
Mode 0
15 14
6
5
4
BICK
3
2
1
0
15
14
15
14
0
15 14
0
Don’t care
Don’t care
15:MSB, 0:LSB
15
14
6
5
4
3
2
1
0
Lch Data
Rch Data
Figure 12. Mode 0 Timing (BCKP bit = “0”, LRP bit = “0”)
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相關代理商/技術參數(shù) |
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|---|---|
| AK4342EN | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit Stereo DAC with HP-AMP & 2V Line-Out |
| AK4342EN-L | 制造商:ASAHI 功能描述: |
| AK4342ENP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
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