
[AK4184] 
MS0603-E-00 
 2007/04 
14
■
Digital Interface 
The AK4184 supports a SPI bus system. The Host processor starts to communicate with the serial clock. The digital 
interface can be operated from 1.6V, which enables connecting with a low voltage host controller. The full scale level 
of the digital I/O voltage is specified IOVDD.  
IOVDD 
μ
P 
AK4184 
TP Interface 
KP Interface 
GPIO port 
BRCONT 
SCLK 
DIN 
DOUT 
AVDD=2.5V ~ 3.6V 
XP 
X-Plate (Top side) 
Y-Plate (Bottom side)
YP 
Touch Panel 
PENIRQN
KEYIRQN
6 x 5 
KEYPAD 
8 GPIO 
CSN 
LED Driver 
XN 
YN 
IOVDD=1.6V~AVDD 
Figure7. Typical peripheral connection diagram 
The AK4184 is controlled by reading from and writing to registers through the 4-wire serial interface (CSN, SCLK, 
DIN, and DOUT pins). Data is composed of the control command, control data, and readout data. The transmitter 
sends each bit on the falling edge of SCLK pin and the receiver latches on the rising edge of SCLK. The first 16 bits 
after the falling edge of CSN pin contains the control command followed by 16 bits of control data during the write 
operation, or 16 bits of readout data during the read operation before the rising edge of the CSN. This completes a 
write or read operation. The max clock speed of the SCLK pin is 5MHz. The register value is reset by pulling 
RESETN pin to “L”. 
The control command layout is shown in Table 2. The upper 8-bit word is the touch screen control command. The 
next lower 8-bits [D7:D0] are filled with “0” when accessing the touch screen block. The lower 8 bit word is 
composed of other block control commands, which specify control of the Keypad, GPIO, and PWM output. When 
accessing touch panel functions, the lower 8-bit word [D7:D0] is filled with “0” data. When accessing Keypad, GPIO, 
or PWM control, the upper 8-bit word [D15:D8] is filled with “0” data. 
This command begins with the S bit which specifies access to the touch screen block. The S bit must be set to “1”. 
The touch screen command begins with the A1:A0 bits, which select the measurement axis (X, Y, and Z). The PD bit 
specifies power down control of the touch screen driver and the A/D converter. When controlling other blocks, the 
first bit is a W/R bit, which specifies the direction of data flow on the bus. The next bit specifies the page bit of the 
register, which is the data register and the control register as shown in Table 3. The data of the next 6 bits are the 
address specified in the register. The page and address of the register is shown in Table 4. The next 16 bits are data 
that are read from or written to the register in Table 4. 32 SCLK cycles are necessary for both read and write 
operations.