參數(shù)資料
型號: AK4126VQ
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 6ch 192kHz / 24-Bit Asynchronous SRC
中文描述: 6通道192kHz的/ 24位異步鋼骨混凝土
文件頁數(shù): 23/27頁
文件大小: 241K
代理商: AK4126VQ
ASAHI KASEI
[AK4126]
MS0544-E-00
2006/09
- 23 -
1.
Grounding and Power Supply Decoupling
The AK4126 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD
are supplied separately, the power up sequence is not critical
. AVSS and DVSS must be connected to the same
ground plane.
Decoupling capacitors should be as near to the AK4126 as possible, with the small value ceramic
capacitor being the nearest.
2.
Jitter Tolerance
Figure 17 shows the jitter tolerance to ILRCK and IBICK for AK4126. The jitter frequency and the jitter amplitude shown
in Figure 17 define the jitter quantity. When the jitter amplitude is 0.01Uipp or less, the AK4126 operate normally
regardless of the jitter frequency.
(1) Normal operation
(2) There is a possibility that the distortion degrades. (It may degrade up to about
50dB.)
(3) There is a possibility that the output data is lost.
Note:
- When PLL2-0 = “L/L/L”, “L/L/H”, “L/H/L”, the jitter amplitude is for ILRCK and 1UI (Unit Interval) is one
cycle of ILRCK. When FSI = 48kHz, 1UI is 1/48kHz = 20.8
μ
s.
- When PLL2-0 = “H/*/*” (*: Don’t care), the jitter amplitude is for IBICK and 1UI (Unit Interval) is one cycle of
IBICK. When FSI = 48kHz, 1UI is 1/(64 x 48kHz) = 326ns.
Figure 17. Jitter Tolerance
AK4125 Jitter Tolerance
0.00
0.01
0.10
1.00
10.00
1
10
100
1000
10000
Jitter Frequency [Hz]
A
(3)
(2)
(1)
相關PDF資料
PDF描述
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相關代理商/技術參數(shù)
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