參數(shù)資料
型號(hào): AK4126VQ
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 6ch 192kHz / 24-Bit Asynchronous SRC
中文描述: 6通道192kHz的/ 24位異步鋼骨混凝土
文件頁(yè)數(shù): 20/27頁(yè)
文件大小: 241K
代理商: AK4126VQ
ASAHI KASEI
[AK4126]
MS0544-E-00
2006/09
- 20 -
Internal Reset Function for Clock Change
The change of the clock supplied to the AK4126 is shown in Figure 14. SDTO shows SDTO1, SDTO2 and SDTO3.
External clocks
(Input port
or Output port)
PLL lock &
fs detection
Power-down
Clocks 1
SDTO
(Internal state)
Normal operation
Normal operation
Clocks 2
Don’t care
< 100ms
SMUTE (Note2,
recommended)
(1)
Att.Level
0dB
-
dB
Normal data
Normal data
(1)
PDN pin
Note1
(1) Soft mute cycle. (See Table 6)
E.g. SMT1 pin = “L”, SMT0 pin = “L”, fso = 48kHz
Soft mute cycle: 1024/fso = 21.3ms
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” from GD before PDN pin goes
“L”, which will cause the data on SDTO to remain “0”.
Note 2. SMUTE can also be used to remove the unknown data.
Figure 14. Sequence of changing clocks
UNLOCK pin
The UNLOCK pin outputs “L” when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin
outputs “H”. When PDN pin = “L”, the UNLOCK pin outputs “H”.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4126VQP 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:6CH 192KHZ / 24-BIT ASYNCHRONOUS SRC
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