參數(shù)資料
型號: AK4125VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 192kHz / 24Bit High Performance Asynchronous SRC
中文描述: 192kHz的/ 24位高性能異步鋼骨混凝土
文件頁數(shù): 19/26頁
文件大?。?/td> 393K
代理商: AK4125VF
[AK4125]
PLL Loop Filter
The C1 and R should be connected in series and attached between FILT pin and AVSS in parallel with C2. (Figure 14,
Table 6, Table 7) Please be careful the noise onto the FILT pin. When using IBICK, the value of external element is not
dependent on the IBICK input frequency.
AK4125
C1
R
FILT
AVSS
C2
Figure 14. PLL Loop Filter
[Input PORT in slave mode]
1. When using ILRCK
PLL2
L
PLL1
L
PLL0
L
ILRCK
8k
96kHz
8k
216kHz
16k
216kHz
8k
216kHz
16k
216kHz
Table 6. PLL Loop Filter (ILRCK Mode)
C2 [nF]
0.68
±
30%
2.2
±
30%
0.68
±
30%
2.2
±
30%
0.68
±
30%
R [
Ω
]
1.8k
±
5%
1k
±
5%
1.5k
±
5%
1k
±
5%
1.5k
±
5%
C1 [
μ
F]
0.68
±
30%
1.0
±
30%
0.68
±
30%
1.0
±
30%
0.68
±
30%
L
L
H
L
H
L
- Note. Smaller value can be selected for the capacitors (C1, C2) in case of ILRCK range from 16kHz to 216kHz..
2. When using IBICK
PLL2
PLL1
PLL0
ILRCK
H
*
*
8k
216kHz
Table 7. PLL Loop Filter (IBICK Mode, *: Don’t care)
Note. The IBCIK must be continuous except when the clocks are changed.
Note. IBCIK = 32fsi is supported only 16bit LSB justified and I
[Input PORT in master mode]
1. When IMCLK is 256fs, 384fs, 512fs or 768fs, any external parts shown in
2. When IMCLK is 128fs or 192fs, the external parts shown in
C2 [nF]
1.0
±
30%
R [
Ω
]
470
±
5%
C1 [
μ
F]
0.22
±
30%
2
S Compatible.
Figure 14 are not required.
Table 7 are required.
MS0379-E-04
2007/07
- 19 -
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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