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參數(shù)資料
| 型號： | AK4125VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192kHz / 24Bit High Performance Asynchronous SRC |
| 中文描述： | 192kHz的/ 24位高性能異步鋼骨混凝土 |
| 文件頁數(shù)： | 12/26頁 |
| 文件大?。?/td> | 393K |
| 代理商： | AK4125VF |
[AK4125]
OPERATION OVERVIEW
■
System Clock & Audio Interface Format for Input PORT
The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK
(Mode 0
～
2 of Table 2) or IBICK (Mode 4
～
7 of Table 2) in slave mode. The MCLK is not needed in slave mode. And
an internal system clock is created by IMCLK (Mode 8
～
15 of Table 2) in master mode. The PLL2-0 pins and IDIF2-0
pins select the master/slave and PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when the PDN pin =
“L”.
The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2’s compliment format.
The SDTI is latched on the rising edge of IBICK. Select the audio interface format when the PDN pin = “L”. When in
BYPASS mode, both IBICK and OBICK are fixed to 64fs.
Mode IDIF2 IDIF1 IDIF0
SDTI Format
0
L
L
L
16bit, LSB justified
1
L
L
H
20bit, LSB justified
2
L
H
L
24/20bit, MSB justified
3
L
H
H
24/16bit, I
2
S Compatible
4
H
L
L
24bit, LSB justified
5
H
L
H
24bit, MSB justified
6
H
H
L
24bit, I
2
S Compatible
7
H
H
H
Table 1. Input Audio Interface Format (Input PORT)
ILRCK
IBICK
IBICK Freq
≥
32fsi
≥
40fsi
≥
48fsi
≥
48fsi or 32fsi
≥
48fsi
64fs
64fs
Master / Slave
Input
Input
Slave
Output
Output
Master
Reserved
SMUTE
Note 13)
(
Mode
Master / Slave
PLL2
PLL1
PLL0
ILRCK Freq
IBICK Freq
IMCLK
0
1
L
L
L
L
L
H
8k
～
96kHz
8k
～
216kHz
16k
～
216kHz
(Note 9)
Manual
Depending on
IDIF2-0
Note 10)
(
Not
needed.
Note 12)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Table 2. PLL Setting (Input PORT)
L
H
L
H
L
H
L
H
L
H
L
H
L
H
(
Semi-Auto
Slave
Reserved
IMCLK = DVSS
IBICK = Input
ILRCK = Input
32fsi (Note 11)
64fsi
128fsi
64fsi
Manual
Not
needed.
Note 12)
8k
～
216kHz
Note 10)
(
(
Semi-Auto
128fs
256fs
512fs
128fs
192fs
384fs
768fs
192fs
8k
～
216kHz
8k
～
108kHz
8k
～
54kHz
8k
～
216kHz
8k
～
216kHz
8k
～
108kHz
8k
～
54kHz
8k
～
216kHz
Manual
Semi-Auto
Master
IMCLK = Input
IBICK = Output
ILRCK = Output
64fs
Manual
Semi-Auto
Note 9. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter”.
Note 10. IBCIK must be continuous except when the clocks are changed.
Note 11. IBCIK = 32fsi is supported only 16bit LSB justified and I
Note 12. Fixed to DVSS.
Note 13. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode.
2
S Compatible.
MS0379-E-04
2007/07
- 12 -
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