參數資料
型號: AK4115
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: High Feature 192kHz 24bit Digital Audio Interface Transceiver
中文描述: 高功能192kHz的24位數字音頻接口收發(fā)器
文件頁數: 19/64頁
文件大?。?/td> 606K
代理商: AK4115
ASAHI KASEI
[AK4115]
MS0573-E-00
2006/12
- 19 -
2. Asynchronous Mode: ASYNC bit = “1”, PSEL = “0”
When ASYNC bit is “1”, DIT and DIR can operate at different sample rates(non-multiples). In Mode1, Mode2 (When
the PLL is the unlock state) and Mode3, SDTO is fixed “L”. The input timing of DAUX should be synchronized with
ELRCK and EBCIK. The master clock of TX can be selected to either X’tal or EMCK by the MSEL bit (See Table 4).
MSEL bit
Master Clock
0
X’tal
1
EMCK
Table 4. Master clock setting for TX in asynchronous mode.
Defalut
RX
Clock
I/O
TX
Mode
CM1
CM0
UNLOCK
PLL
Status
X'tal
Status
Clock
Source
SDTO
Clock
Source
X’tal
or
EMCK
(Note 22)
X’tal
or
EMCK
X’tal
or
EMCK
X’tal
or
EMCK
X’tal
or
EMCK
Clock
I/O
0
0
0
-
ON
ON
(Note 19)
PLL
(RX)
Note 20
RX
Note 21
1
0
1
-
OFF
ON
X'tal
Note 20
“L”
Note 21
0
ON
ON
PLL
(RX)
Note 20
RX
Note 21
2
1
0
1
ON
ON
X'tal
Note 20
“L”
Note 21
3
1
1
-
ON
ON
X'tal
Note 20
“L”
Note 21
Note 18. ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note 19 When the X’tal is not used as clock comparison for sampling frequency detection (i.e. XTL1,0 = “1,1”), the
X’tal is OFF.
Note 20: MCKO1/2, BICK, LRCK
Note 21. EMCK or X’tal, EBICK, ELRCK, DAUX
Note 22. When X’tal is OFF, the clock source supports EMCK only.
Table 5. Clock operation for DIT/DIR in asynchronous mode
XTI1
Input
Selector
Clock
Recovery
Clock
Generator
DAIF
Decoder
DEM
Audio I/F
for RX
X'tal
Oscillator
LRCK
BICK
SDTO
EMCK
MCKO2
XTO1
MCKO1
RX1
RX2
RX3
RX4
RX5
RX6
RX7
DIT
TX0
TXP1
TXN1
8 to 3
RXN0
RXP0
X'tal
Oscillator
XTO2
Clock Selector
(CM1-0)
ACKS
XTI2
XSEL
Audio I/F
for TX
ELRCK
EBICK
DAUX
“L”
MSEL
Figure 16. Clocks for DIT/DIR in asynchronous mode
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