參數(shù)資料
型號(hào)： AK4113VF
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 192KHZ 24BIT DIR WITH 6:1 SELECTOR
中文描述： 192kHz 24位處長(zhǎng)與6:1選擇器
文件頁(yè)數(shù)： 32/49頁(yè)
文件大小： 531K
代理商： AK4113VF
ASAHI KASEI
[AK4113]
MS0349-E-01
2005/03
- 32 -
Serial
Control
Interface
1. 4-wire serial control mode (I2C pin = “L”)
The internal registers may be either written or read by the 4-wire
μ
P interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, C1-0 are fixed to “00”), Read/Write (1-bit), Register address (MSB
first, 5-bits) and Control data (MSB first, 8-bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition
of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the registers to their default values.
CDTI
CCLK
CSN
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CDTO
Hi-Z
WRITE
CDTI
C1
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CDTO
Hi-Z
READ
D4
D5
D6
D7
D0
D1
D2
D3
Hi-Z
C1,C0: Chip Address (Fixed to “00”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 31. 4-wire Serial Control I/F Timing
* The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN pin
is “L”.
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