參數(shù)資料
型號: AK4113VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 192KHZ 24BIT DIR WITH 6:1 SELECTOR
中文描述: 192kHz 24位處長與6:1選擇器
文件頁數(shù): 25/49頁
文件大?。?/td> 531K
代理商: AK4113VF
ASAHI KASEI
[AK4113]
MS0349-E-01
2005/03
- 25 -
Error Handing
The following nine events cause the INT0 and INT1 pins to show the status of the interrupt condition. When the PLL is
OFF (Clock Operation Mode 1), INT0 and INT1 pins go to “L”.
1. UNLCK : PLL unlock state detect
“1” when the PLL loses lock. The AK4113 loses lock when the distance between two preamble is
not correct or when those preambles are not correct.
2. PAR : Parity error or bi-phase coding error detection
“1” when parity error or bi-phase coding error is detected, updated every sub-frame cycle.
3. AUTO : Non-Linear PCM or DTS-CD Bit Stream detection
The OR function of NPCM and DTSCD bits is available at the AUTO bit.
4. V : Validity flag detection
“1” when validity flag is detected. Updated every sub-frame cycle.
5. AUDION : Non-audio detection
“1” when the “AUDION” bit in recovered channel status indicates “1”. Updated every block cycle.
6. STC : Sampling frequency or pre-emphasis information change detection
When either FS3-0 bit or PEM bit is changed, it maintains “1” during 1 sub-frame.
7. QINT : U-bit Sync flag
“1” when the Q-subcode differs from the old one. Updated every sync code cycle for Q-subcode.
8. CINT : Channel status sync flag
“1” when received C bit differs from the old one. Updated every block cycle.
9. DAT : DAT Start ID detect
“1” when the category code indicates “DAT” and “DAT Start ID” is detected. When DCNT bit is
“1”, it does not indicate “1” even if “DAT Start ID” is detected again within “3841 x LRCK”.
When “DAT Start ID” is detected again after “3840 x LRCK” passed, it indicates “1”. When
DCNT bit is “0”, it indicates “1” every “DAT Start ID” detection.
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