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參數(shù)資料
| 型號： | AK2540 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Quad T1 Transceiver |
| 中文描述： | 的4 T1收發(fā)器 |
| 文件頁數(shù)： | 18/33頁 |
| 文件大?。?/td> | 159K |
| 代理商： | AK2540 |
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ASAHI K ASEI [AK2540]
MS0012-E-00 2000/1
18
THEORY OF OPERATION
Mode of Operation
There are two mode of operation as selected by HWMODE pin. One is the hardware mode and the
other is the host mode.
The device is in the hardware mode when HWMODE pin is pulled high and in the host mode when
HWMODE pin is pulled low.
Minimum information is available in hardware mode. In Hardware Mode, the device is controlled
by the appropriate pins. In Host Mode, the device is controlled by appropriate registers described
after through parallel interface.
In Host Mode, all interrupt can be masked by appropriate mask register. However, the status
registers and hard flag pins show the current status regardless of the mask register setting.
Pulse Shape Control (Hardware Mode and Host Mode)
In Hardware Mode, the transmit pulse shape in channel x (x = 1,2,3 and 4) is determined by Line
Length control pins LENG0x through LENG2x as shown in Table 1.
Table 1. Line Length Control
LENG2x
LENG1x
LENG0x
Line Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
0-133feet
133-266feet
266-399feet
399-533feet
533-655feet
Reserved
Reserved
X=1,2,3 and 4
In Host Mode, the transmission pulse shape is determined by appropriate register described in the
Register Description section later
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