參數(shù)資料
型號: AK2305
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: Dual PCM CODEC for ISDN TERMINAL ADAPTER
中文描述: 雙PCM編解碼器的ISDN終端適配器
文件頁數(shù): 9/43頁
文件大?。?/td> 481K
代理商: AK2305
ASAHI K ASEI [AK 2305]
C0029-E-02 9 1999/8
FUNCTIONAL DESCRIPTION
PCM INTERFACE
AK2305 supports the following types of format.
One of those is selected by PCMIF0 and PCMIF1 registers.
- L ong F rame Sync(L F )
- Short F rame Sync(SF )
- GC I
- IDL
PCM data of both channels are multiplexed and interfaced through the common pins (DR0, DX0) in 2ch
Multiplex I/F mode. But in 2ch Independent I/F mode of LF or SF, it is also available to interface through the
independent pin(DR0/1,DX0/1) by channel.
Register of PCM interface mode selection
PCMIF1
PCMIF0
Interface
Frame sync
Input pin
Output pin
Remarks
0
0
LF/SF (Non multiplex)
FS0,FS1
DR0,DR1
DX0, DX1
Reset
0
1
LF/SF (2ch multiplex)
FS0,FS1
DR0
DX0
1
0
GCI (2ch multiplex)
FS0
DR0
DX0
1
1
IDL (2ch multiplex)
FS0
DR0
DX0
FRAME SYNC SIGNAL(Frame Sync : FS)
Frame sync signal should be 8kHz clock. 8bits PCM data is accommodated in 1 frame (125us).
Though only FS0 is required (FS1 isn’t required) in the mode of GCI or IDL, both FS0 and FS1 are required in
the mode of LF or SF.
FIRST FS
It is used as the input clock of PLL. PLL generates all timing in this IC from this signal.
FS0 is assigned as First FS in the mode of GCI or IDL, and in the mode of LF or SF, it is assigned by the first FS
register.
1stFS
register
First FS
Remarks
0
FS0
Reset
1
FS1
Note
K eep supplying the first FS except for the state of all power down(PD=”H”). If the first FS is not supplied,
AK2305 loses timing; at a result, DTMFR and TONE GEN become not guaranteed to work normally.
BCLK
This clock decides the PCM data rate. See the following table of the relation between BCLK and PCM data rate.
PCM I/F mode
BCLK
Rate of PCM
data
LF/SF/IDL
F
F
GCI
2F
F
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