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參數(shù)資料
| 型號(hào)： | AHA4013B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12.5 MBytes/sec Reed-Solomon Error Correction Device |
| 中文描述： | 12.5 MB /秒的Reed - Solomon糾錯(cuò)裝置 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 232K |
| 代理商： | AHA4013B |
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PS4013B-0600
Page 13 of 24
Advanced Hardware Architectures, Inc.
Figure 6:
CLK Characteristics
All timing diagrams in this specification use the clock at the CLK pin as the reference point.
3.2
INITIALIZATION
This section describes the Reset and Initialization Sequence timing. For a detailed discussion on these
sequences, refer to Section 2.6
Reset and Initialization Sequence
.
Figure 7:
Initialization and Reset Timing
Initialization bytes are strobed into the device
while RSTN and DSIN are low during rising edges
of CLK. The RSTN must be active low for at least
two clocks before the first initialization byte is
strobed in and remain active for at least one clock
after the final byte. Initialization register data may
be strobed at a minimum of 1 clock per byte. After
power-on the initializing registers
’
contents are
undefined.
For a detailed description of the Initialization
Registers, refer to Section 2.6
Reset and
Initialization Sequence
.
3.3
DATA INPUT
The chip latches the input data on the DI pins on
the rising edge of the CLK when DSIN and RDYIN
are both active. The two figures below show the
timing diagrams for buffer Ready and buffer Not
Ready conditions.
NUMBER
1
2
3
4
5
DESCRIPTION
MINIMUM
MAXIMUM
5
UNITS
nsec
nsec
nsec
nsec
nsec
CLK rise time
CLK high time
CLK fall time
CLK low time
CLK period
8
5
8
20
NUMBER
1
2
3
DESCRIPTION
MINIMUM
7
0
2
MAXIMUM
UNITS
nsec
nsec
Clock cycles
RSTN and DSIN setup time
RSTN and DSIN hold time
RSTN and DSIN assertion
CLK
1
2
3
4
5
1
1
1 2
2
2
3
6
1
4
5
CLK
DI
DSIN
RSTN
at least 2
clock cycles
Input 6 bytes data for initialization
RESET
at least 1
clock cycle
Data
at least 2
clock cycles
3
INITIALIZE
DSON
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