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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AGLP125V2-CSG289I |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 101/134闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA IGLOO PLUS 125K 289-CSP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 152 |
| 绯诲垪锛� | IGLOO PLUS |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 3120 |
| RAM 浣嶇附瑷�(j矛)锛� | 36864 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 212 |
| 闁€鏁�(sh霉)锛� | 125000 |
| 闆绘簮闆诲锛� | 1.14 V ~ 1.575 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 289-TFBGA锛孋SBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 289-CSP锛�14x14锛� |
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IGLOO PLUS Low Power Flash FPGAs
Revision 16
2-55
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-20 Timing Model and Waveforms
PRE
CLR
Out
CLK
Data
EN
tSUE
50%
tSUD
tHD
50%
tCLKQ
0
tHE
tRECPRE
tREMPRE
tRECCLR
tREMCLR
tWCLR
tWPRE
tPRE2Q
tCLR2Q
tCKMPWH tCKMPWL
50%
Table 2-82 Register Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
Std.
Units
tCLKQ
Clock-to-Q of the Core Register
0.89
ns
tSUD
Data Setup Time for the Core Register
0.81
ns
tHD
Data Hold Time for the Core Register
0.00
ns
tSUE
Enable Setup Time for the Core Register
0.73
ns
tHE
Enable Hold Time for the Core Register
0.00
ns
tCLR2Q
Asynchronous Clear-to-Q of the Core Register
0.60
ns
tPRE2Q
Asynchronous Preset-to-Q of the Core Register
0.62
ns
tREMCLR
Asynchronous Clear Removal Time for the Core Register
0.00
ns
tRECCLR
Asynchronous Clear Recovery Time for the Core Register
0.24
ns
tREMPRE
Asynchronous Preset Removal Time for the Core Register
0.00
ns
tRECPRE
Asynchronous Preset Recovery Time for the Core Register
0.23
ns
tWCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.30
ns
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.30
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core Register
0.56
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.56
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
鐩搁棞(gu膩n)PDF璩囨枡 |
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|---|---|
| AGLP125-V2CSG289PP | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125-V2FCS289 | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125-V2FCS289ES | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125-V2FCS289I | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125-V2FCS289PP | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
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