參數(shù)資料
型號(hào): AGLP-EVAL-KIT
廠商: Microsemi SoC
文件頁(yè)數(shù): 3/27頁(yè)
文件大?。?/td> 0K
描述: KIT EVAL HARDWARE FOR AGLP
標(biāo)準(zhǔn)包裝: 1
系列: IGLOO PLUS
類型: FPGA
適用于相關(guān)產(chǎn)品: AGLP125
所含物品: 板,電纜,DVD,跳線,電源,編程器
其它名稱: 1100-1137
11
www.microsemi.com/soc
ProASIC3
ProASIC3 nano
The lowest-cost solution with enhanced I/O capabilities
Microsemi’s innovative ProASIC3 nano devices bring a new level of value and flexibility to high-volume markets. When measured against the typical project
metrics of performance, cost, flexibility and time-to-market, ProASIC3 nano devices provide an attractive alternative to ASICs and ASSPs in fast moving or highly
competitive markets. Customer-driven total system cost reduction was a key design criterium for the ProASIC3 nano program. Reduced device cost, availability of
known good die, a single-chip implementation and a broad selection of small footprint packages all contribute to lower total system costs.
1.5Vcoreforlowpower
Knowngooddiesupported
350MHzsystemperformance
EmbeddedSRAMNVM
Configurationmemoryerrorimmune
Enhancedcommercialtemperature
EnhancedI/Ofeatures
ISPandsecurity
Reprogrammableflashtechnology
Zerolead-timeonselecteddevices
CCCsandPLLs
I/Os Per Package
ProASIC3 nano Devices
A3PN010
A3PN020
A3PN060
A3PN125
A3PN250
System Gates
10,000
20,000
60,000
125,000
250,000
Typical Equivalent Macrocells
86
172
512
1,024
2,048
VersaTiles(D-flip-flops)
260
520
1,536
3,072
6,144
RAM1(1,024bits)
18
36
4,608-BitBlocks1
4
8
FlashROMKbits(1,024bits)
1
AES-Protected ISP1
Yes
Integrated PLL in CCCs1
1
VersaNetGlobals
4
18
I/OBanks
2
3
2
4
Maximum User I/Os (packaged device)
34
49
71
68
Known Good Die User I/Os
34
52
71
68
Package Pin
QN
VQ
QN48
QN68
VQ100
ProASIC3 nano Devices
A3PN010
A3PN020
A3PN060
A3PN125
A3PN250
Known Good Die
34
52
71
68
QN48
34
QN68
49
VQ100
71
68
Notes:
1. A3PN030 and smaller devices do not support this feature.
2. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E datasheets and FPGA fabric user’s guides.
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