參數(shù)資料
型號： AGLP-EVAL-KIT
廠商： Microsemi SoC
文件頁數(shù)： 2/27頁
文件大小： 0K
描述： KIT EVAL HARDWARE FOR AGLP
標準包裝： 1
系列： IGLOO PLUS
類型： FPGA
適用于相關(guān)產(chǎn)品： AGLP125
所含物品： 板，電纜，DVD，跳線，電源，編程器
其它名稱： 1100-1137
10
ProASIC3
ProASIC3/E
I/Os Per Package
Thelowpower,low-costFPGAsolution
The ProASIC3 series of flash FPGAs offers a breakthrough in power, price, performance, density and features for today’s most demanding high-volume applications.
ProASIC3 devices support the ARM Cortex-M1 processor, offering the benefits of programmability and time-to-market at low cost. ProASIC3 devices are based
on nonvolatile flash technology and support 30,000 to 3,000,000 gates and up to 620 high-performance I/Os. For automotive applications, selected ProASIC3
devices are qualified to the AEC-Q100 and are available with AEC T1 screening and PPAP documentation.
ProASIC3
Devices
A3P030 A3P060 A3P125
A3P250
A3P400
A3P600
A3P1000
A3PE600
A3PE1500
A3PE3000
Cortex-M1
Devices
M1A3P250*
M1A3P400
M1A3P600
M1A3P1000
M1A3PE1500
M1A3PE3000
I/O Type
Single-
Ended
I/O
Single-
Ended
I/O
Single-
Ended
I/O
Single-
Ended
I/O
Differen-
tial I/O
Pairs
Single-
Ended
I/O
Differen-
tial I/O
Pairs
Single-
Ended
I/O
Differen-
tial I/O
Pairs
Single-
Ended
I/O
Differen-
tial I/O
Pairs
Single-
Ended
I/O
Differen-
tial I/O
Pairs
Single-
Ended
I/O
Differen-
tial I/O
Pairs
Single-
Ended
I/O
Differen-
tial I/O
Pairs
QN48
34
—
QN68
49
—
QN132
81
80
84
87
19
—
CS121
—
96
—
VQ100
77
71
68
13
—
TQ144
—
91
100
—
PQ208
—
133
151
34
151
34
154
35
154
35
147
65
147
65
147
65
FG144
—
96
97
24
97
25
97
25
97
25
—
FG256
—
157
38
178
38
177
43
177
44
165
79
—
FG324
—
221
110
FG484
—
194
38
235
60
300
74
270
135
280
139
341
168
FG676
—
444
222
—
FG896
—
620
310
Notes:
1. AES is not available for Cortex-M1 ProASIC3 devices.
2. Available as automotive “T” grade
3. The M1A3P250 device does not support this package.
Note:
* M1A3P250 does not support the FG256 and QN132 packages.
ProASIC3/E Devices
A3P030
A3P060
A3P125
A3P250
A3P400
A3P600
A3P1000
A3PE600
A3PE1500
A3PE3000
Cortex-M1Devices
M1A3P250
M1A3P400
M1A3P600
M1A3P1000
M1A3PE1500
M1A3PE3000
System Gates
30,000
60,000
125,000
250,000
400,000
600,000
1,000,000
600,000
1,500,000
3,000,000
Typical Equivalent
Macrocells
256
512
1,024
2,048
—
VersaTiles(D-flip-flops)
768
1,536
3,072
6,144
9,216
13,824
24,576
13,824
38,400
75,264
RAM(1,024bits)
—
18
36
54
108
144
108
270
504
4,608-BitBlocks
—
4
8
12
24
32
24
60
112
FlashROMKbits
(1,024bits)
1
AES-Protected ISP1
—
Yes
Integrated PLL in CCCs
—
1
6
VersaNetGlobals
6
18
I/OBanks
2
4
8
Maximum User I/Os
(packaged device)
81
96
133
157
194
235
300
270
444
620
Package Pins
QFN
CS
VQ
TQ
PQ
FG
QN48
QN68
QN132
VQ100
QN132
CS121
VQ1002
TQ144
FG1442
QN1322
VQ1002
TQ144
PQ208
FG1442
QN1322, 3
VQ1002
PQ208
FG1442
FG2562, 3
PQ208
FG144
FG256
FG484
PQ208
FG144
FG256
FG484
PQ208
FG1442
FG2562
FG4842
PQ208
FG256
FG484
PQ208
FG484
FG676
PQ208
FG324
FG484
FG896
Lowpower
Singlechip,singlevoltage
Nonvolatile,reprogrammable
Lowcost
Liveatpower-up
Maximumdesignsecurity
Configurationmemoryerrorimmune
Clockmanagement
AdvancedI/Ostandards
UsernonvolatileFlashROM
SecureISP
Highperformance
ProASIC3/E Devices
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