2-6 Revision 17 Thermal Characteristics Introduction The temperature variable in the Microsemi " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGLN125V5-ZVQ100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 66/150闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA NANO 1KB 125K 100VQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� IGLOO nano
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 3072
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 71
闁€鏁�(sh霉)锛� 125000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
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IGLOO nano DC and Switching Characteristics
2-6
Revision 17
Thermal Characteristics
Introduction
The temperature variable in the Microsemi Designer software refers to the junction temperature, not the
ambient temperature. This is an important distinction because dynamic and static power consumption
cause the chip junction temperature to be higher than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
TJ = Junction Temperature = T + TA
EQ 1
where:
TA = Ambient temperature
T = Temperature gradient between junction (silicon) and ambient T = ja * P
ja = Junction-to-ambient of the package. ja numbers are located in Figure 2-5.
P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is
jc and the junction-to-ambient air thermal resistivity is
ja. The thermal characteristics for ja are shown for two air flow rates. The maximum operating junction
temperature is 100掳C. EQ 2 shows a sample calculation of the maximum operating power dissipation
allowed for a 484-pin FBGA package at commercial temperature and in still air.
EQ 2
Temperature and Voltage Derating Factors
Maximum Power Allowed
Max. junction temp. (
C) Max. ambient temp. (C)
鈥�
ja(C/W)
------------------------------------------------------------------------------------------------------------------------------------------
100
C70C
鈥�
20.5掳C/W
-------------------------------------
1.46 W
=
Table 2-5
Package Thermal Resistivities
Package Type
Pin
Count
jc
ja
Units
Still Air
200 ft./
min.
500 ft./
min.
Chip Scale Package (CSP)
36
TBD
C/W
81
TBD
C/W
Quad Flat No Lead (QFN)
48
TBD
C/W
68
TBD
C/W
100
TBD
C/W
Very Thin Quad Flat Pack (VQFP)
100
10.0
35.3
29.4
27.1
C/W
Table 2-6
Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70掳C,
VCC = 1.425 V)
For IGLOO nano V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Array Voltage
VCC (V)
Junction Temperature (掳C)
鈥�40掳C
鈥�20掳C
0掳C
25掳C
70掳C
85掳C
100掳C
1.425
0.947
0.956
0.965
0.978
1.000
1.009
1.013
1.5
0.875
0.883
0.892
0.904
0.925
0.932
0.937
1.575
0.821
0.829
0.837
0.848
0.868
0.875
0.879
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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