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寤犲晢锛� Microsemi SoC
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鏂囦欢澶у皬锛� 0K
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妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� IGLOO nano
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 3072
RAM 浣嶇附瑷堬細 36864
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IGLOO nano DC and Switching Characteristics
2-48
Revision 17
1.2 V DC Core Voltage
Table 2-75 Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
Std. Units
tOCLKQ
Clock-to-Q of the Output Data Register
1.52
ns
tOSUD
Data Setup Time for the Output Data Register
1.15
ns
tOHD
Data Hold Time for the Output Data Register
0.00
ns
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
1.96
ns
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
1.96
ns
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
0.00
ns
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
0.24
ns
tOREMPRE
Asynchronous Preset Removal Time for the Output Data Register
0.00
ns
tORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
0.24
ns
tOWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.19
ns
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
0.19
ns
tOCKMPWH
Clock Minimum Pulse Width HIGH for the Output Data Register
0.31
ns
tOCKMPWL
Clock Minimum Pulse Width LOW for the Output Data Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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