Revision 17 2-85 Timing Characteristics 1.5 V DC Core Voltage Table 2-106 FIFO
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寤犲晢锛� Microsemi SoC
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鏂囦欢澶у皬锛� 0K
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妯�(bi膩o)婧�(zh菙n)鍖呰锛� 714
绯诲垪锛� IGLOO nano
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杓稿叆/杓稿嚭鏁�(sh霉)锛� 23
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闆绘簮闆诲锛� 1.14 V ~ 1.575 V
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IGLOO nano Low Power Flash FPGAs
Revision 17
2-85
Timing Characteristics
1.5 V DC Core Voltage
Table 2-106 FIFO
Worst Commercial-Case Conditions: TJ = 70掳C, VCC = 1.425 V
Parameter
Description
Std.
Units
tENS
REN, WEN Setup Time
1.66
ns
tENH
REN, WEN Hold Time
0.13
ns
tBKS
BLK Setup Time
0.30
ns
tBKH
BLK Hold Time
0.00
ns
tDS
Input Data (WD) Setup Time
0.63
ns
tDH
Input Data (WD) Hold Time
0.20
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
2.77
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
1.50
ns
tRCKEF
RCLK High to Empty Flag Valid
2.94
ns
tWCKFF
WCLK High to Full Flag Valid
2.79
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
10.71
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
2.90
ns
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
10.60
ns
tRSTBQ
RESET Low to Data Out LOW on RD (flow-through)
1.68
ns
RESET Low to Data Out LOW on RD (pipelined)
1.68
ns
tREMRSTB
RESET Removal
0.51
ns
tRECRSTB
RESET Recovery
2.68
ns
tMPWRSTB
RESET Minimum Pulse Width
0.68
ns
tCYC
Clock Cycle Time
6.24
ns
FMAX
Maximum Frequency for FIFO
160
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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