1-6 Revision 17 Flash*Freeze Technology The IGLOO nano device has an ultra-low power static mode, called Flash*F" />
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IGLOO nano Device Overview
1-6
Revision 17
Flash*Freeze Technology
The IGLOO nano device has an ultra-low power static mode, called Flash*Freeze mode, which retains all
SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology
enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the
Flash*Freeze pin while all power supplies are kept at their original values. I/Os, global I/Os, and clocks
can still be driven and can be toggling without impact on power consumption, and the device retains all
core registers, SRAM information, and I/O states. I/Os can be individually configured to either hold their
previous state or be tristated during Flash*Freeze mode.
Alternatively, I/Os can be set to a specific state using weak pull-up or pull-down I/O attribute
configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device
consumes as little as 2 W in this mode.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide
when it is safe to transition to this mode. Refer to Figure 1-5 for an illustration of entering/exiting
Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode
usage is not planned.
VersaTiles
The IGLOO nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS
core tiles. The IGLOO nano VersaTile supports the following:
All 3-input logic functions鈥擫UT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-6 for VersaTile configurations.
Figure 1-5 IGLOO nano Flash*Freeze Mode
Figure 1-6 VersaTile Configurations
IGLOO nano
FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
X1
Y
X2
X3
LUT-3
Data
Y
CLK
Enable
CLR
D-FF
Data
Y
CLK
CLR
D-FF
LUT-3 Equivalent
D-Flip-Flop with Clear or Set
Enable D-Flip-Flop with Clear or Set
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ABC40DRAH CONN EDGECARD 80POS .100 R/A DIP
A3PN010-QNG48I IC FPGA NANO 10K GATES 48-QFN
GMC65DRTI-S13 CONN EDGECARD 130POS .100 EXTEND
HBC60DRAN CONN EDGECARD 120PS R/A .100 SLD
HBC60DRAH CONN EDGECARD 120PS R/A .100 SLD
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