參數(shù)資料
型號： AGLE3000V2-FFG484C
元件分類： FPGA
英文描述： FPGA, 75264 CLBS, 3000000 GATES, PBGA484
封裝： 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件頁數(shù)： 95/156頁
文件大?。?/td> 5023K
代理商： AGLE3000V2-FFG484C
IGLOOe DC and Switching Characteristics
Ad vance v0.3
2-29
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS
standard is supported as part of the 3.3 V LVTTL support.
Table 2-33 Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL
IIH
Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2
4 mA
–0.3
0.8
2
3.6
0.4
2.4
4
25
27
10
8 mA
–0.3
0.8
2
3.6
0.4
2.4
8
51
54
10
12 mA
–0.3
0.8
2
3.6
0.4
2.4
12
103
109
10
16 mA
–0.3
0.8
2
3.6
0.4
2.4
16
132
127
10
24 mA
–0.3
0.8
2
3.6
0.4
2.4
24
268
181
10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Figure 2-7 AC Loading
Table 2-34 AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point*
(V)
VREF (typ.) (V)
CLOAD (pF)
03.3
1.4
–
5
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Test Point
Enable Path
Datapath
35 pF
R = 1 k
R to VCCI for tLZ/tZL/tZLS
R to GND for tHZ/tZH/tZHS
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
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