參數(shù)資料
型號： AGLE3000V2-FFG484C
元件分類： FPGA
英文描述： FPGA, 75264 CLBS, 3000000 GATES, PBGA484
封裝： 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件頁數(shù)： 94/156頁
文件大?。?/td> 5023K
代理商： AGLE3000V2-FFG484C
IGLOOe DC and Switching Characteristics
2- 28
Advance v0.3
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 110°C, the short current condition would have to be sustained for more than three
months to cause a reliability concern. The I/O design does not contain any short circuit protection,
but such protection would only be needed in extremely prolonged stress conditions.
Table 2-30 Duration of Short Circuit Event before Failure
Temperature
Time before Failure
–40°C
> 20 years
0°C
> 20 years
25°C
> 20 years
70°C
5 years
85°C
2 years
100°C
6 months
110°C
3 months
Table 2-31 Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)
240 mV
2.5 V LVCMOS (Schmitt trigger mode)
140 mV
1.8 V LVCMOS (Schmitt trigger mode)
80 mV
1.5 V LVCMOS (Schmitt trigger mode)
60 mV
1.2 V LVCMOS (Schmitt trigger mode)
40 mV
Table 2-32 I/O Input Rise Time, Fall Time, and Related I/O Reliability*
Input Buffer
Input Rise/Fall Time (min.)
Input Rise/Fall Time (max.)
Reliability
LVTTL/LVCMOS (Schmitt trigger
disabled)
No requirement
10 ns*
20 years (110°C)
LVTTL/LVCMOS (Schmitt trigger
enabled)
No requirement
No requirement, but input noise
voltage
cannot
exceed
Schmitt
hysteresis.
20 years (110°C)
HSTL/SSTL/GTL
No requirement
10 ns*
10 years (100°C)
LVDS/B-LVDS/M-LVDS/LVPECL
No requirement
10 ns*
10 years (100°C)
* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,
then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the
rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity
evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
相關(guān)PDF資料
PDF描述
AGOF5S3P-20.00MHZ OCXO, CLOCK, 20 MHz, HCMOS OUTPUT
AH110-89G 50 MHz - 2000 MHz RF/MICROWAVE WIDE BAND MEDIUM POWER AMPLIFIER
AH1464 SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 2.6mm, THROUGH HOLE-STRAIGHT
AH1682 SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 2.65mm, PANEL MOUNT
AH1482 SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 2.65mm, THROUGH HOLE-STRAIGHT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGLE3000V2-FFG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FFG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FFG896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FFG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FFGG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*